## An exact solution to simultaneous technology mapping and linear placement problem (1996)

Venue: | Proc. Int'l Conf. on Computer Aided Design |

Citations: | 25 - 7 self |

### BibTeX

@INPROCEEDINGS{Lou96anexact,

author = {Jinan Lou and Amir H. Salek and Massoud Pedram},

title = {An exact solution to simultaneous technology mapping and linear placement problem},

booktitle = {Proc. Int'l Conf. on Computer Aided Design},

year = {1996},

pages = {583--588}

}

### Years of Citing Articles

### OpenURL

### Abstract

In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach. A novel design flow, which extends this algorithm to minimize the circuit delay and handle general DAG structures, is also presented. Experimental results on MCNC benchmarks are reported. I.

### Citations

223 |
Algorithms for VLSI Physical Design Automation
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- 2005
(Show Context)
Citation Context ...ensity) † . The above equation is exact since in one-dimensional routing, there are no vertical constraints and the channel height is set by the maximum clique size in the horizontal constraint graph =-=[17]-=-. Clearly, a is determined from the technology mapping whereas c is determined from the placement. To find the minimum total area A, technology mapping and placement must be done simultaneously. III.2... |

189 | GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization
- Kleinhans, Sigl, et al.
- 1991
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Citation Context ...so use Yannakakis’ MINCUT placement algorithm to do the linear placement in the conventional flow. Otherwise, we would have obtained larger improvements because other placement tools, such as Gordian =-=[8]-=- or TimberWolf [15] do not generate the minimum cut width placement. The suffix of the tree name represents the number of inputs. Our results show an average improvement of 20% in the total post-layou... |

136 | Logic Synthesis and Verification Algorithms
- Hachtel, Somenzi
- 1996
(Show Context)
Citation Context ...lay in section IV. Experimental results and concluding remarks are given in Sections V and VI, respectively. II. Background The problem of technology mapping for general circuit structures is NP-hard =-=[5]-=-. In 1987 Keutzer [7] pointed out the similarity between the library binding problem and the optimal code generation in a compiler. In his algorithm the circuit is partitioned into tree sub-graphs and... |

60 |
TimberWolf 3.2: A new standard cell placement and global routing package
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- 1986
(Show Context)
Citation Context ... MINCUT placement algorithm to do the linear placement in the conventional flow. Otherwise, we would have obtained larger improvements because other placement tools, such as Gordian [8] or TimberWolf =-=[15]-=- do not generate the minimum cut width placement. The suffix of the tree name represents the number of inputs. Our results show an average improvement of 20% in the total post-layout area. In Table II... |

44 | Layout Driven Technology Mapping
- Pedram, Bhat
- 1991
(Show Context)
Citation Context ...ngs of a tree with different area-delay trade-off. Neither of the above-mentioned works considers wiring area or delay during technology mapping. This was the motivation for Pedram and Bhat’s work in =-=[11]-=- to couple technology mapping and placement in order to consider the effect of wires during mapping. Their proposed algorithm assumes that the dynamic programming principle holds during the bottom-up ... |

40 | The Elmore Delay as Bound for RC Trees with Generalized Input Signals
- Gupta, Krauter, et al.
- 1995
(Show Context)
Citation Context ...ibrary cell based on the results from extensive circuit-level simulation using HSpice. For wire delay calculation, the lumped RC model is widely used, but the Elmore delay model gives higher accuracy =-=[4]-=-. The latter model calculates the delay of each wire segment using the equation shown in Figure 5: E rE: wire resistance of E cE: wire capacitance of E CE: total capacitance rooted at E Figure 5. Elmo... |

33 | A near-optimal algorithm for technology mapping minimizing area under delay constraints
- Chaudhary, Pedram
- 1992
(Show Context)
Citation Context ... mapping of the tree in polynomial time. This work was later extended by Rudell [14] to minimum delay technology mapping and by Touati et al. [19] to minimize area mapping under delay constraints. In =-=[1]-=-, Chaudhary and Pedram presented a dynamic programming algorithm to construct the set of all possible mappings of a tree with different area-delay trade-off. Neither of the above-mentioned works consi... |

33 |
Circuit Placement for Predictable Performance
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- 1987
(Show Context)
Citation Context ...ay model. Since the physical location of each block is known, the global wire delays are fairly accurate. Next, the delay budget for each block (tree) is obtained using a technique similar to that of =-=[6]-=-. We use the budget as the constraint to pick up a timing feasible solution from the set of non-inferior solutions generated by SiMPA for each tree. Finally, we refine the floorplan solution to elimin... |

32 |
A polynomial algorithm for the min cut linear arrangement of trees
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- 1985
(Show Context)
Citation Context ...he total length of connecting wire segments. On the other hand, the MINCUT problem is to find a linear placement that minimizes the maximum cut-width. Both problems are NP-hard for the general graphs =-=[21]-=-. In 1979, Shiloach [18] gave an O(n 2.2 ) algorithm to solve the MINSUM problem for trees, and in 1984 Chung [2] improved it to O(n 1.58 ). For MINCUT problems, Lengauer [9] introduced a polynomial t... |

25 |
A New Symbolic Channel Router: YACR2
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- 1985
(Show Context)
Citation Context ...onventional flow and FPD-SiMPA. In the conventional flow, we use SIS to do a minimum delay technology mapping, followed by Gordian and Domino [3] for placement, TimberWolf for global routing and YACR =-=[13]-=- for detailed routing. In FPDSiMPA, we use tree clustering and initial mapping of each tree for block width estimation, followed by Bear-FP [12] which does floorplanning and global routing. Then we ca... |

25 |
A minimum linear arrangement algorithm for undirected trees
- Shiloach
- 1979
(Show Context)
Citation Context ...cting wire segments. On the other hand, the MINCUT problem is to find a linear placement that minimizes the maximum cut-width. Both problems are NP-hard for the general graphs [21]. In 1979, Shiloach =-=[18]-=- gave an O(n 2.2 ) algorithm to solve the MINSUM problem for trees, and in 1984 Chung [2] improved it to O(n 1.58 ). For MINCUT problems, Lengauer [9] introduced a polynomial time algorithm for trees ... |

21 |
DAGON: Technology mapping and local optimization
- Keutzer
- 1987
(Show Context)
Citation Context ...perimental results and concluding remarks are given in Sections V and VI, respectively. II. Background The problem of technology mapping for general circuit structures is NP-hard [5]. In 1987 Keutzer =-=[7]-=- pointed out the similarity between the library binding problem and the optimal code generation in a compiler. In his algorithm the circuit is partitioned into tree sub-graphs and each tree subgraph i... |

19 |
Performance oriented technology mapping
- Touati, Moon, et al.
- 1990
(Show Context)
Citation Context ...ic programming algorithm which finds the minimum gate area mapping of the tree in polynomial time. This work was later extended by Rudell [14] to minimum delay technology mapping and by Touati et al. =-=[19]-=- to minimize area mapping under delay constraints. In [1], Chaudhary and Pedram presented a dynamic programming algorithm to construct the set of all possible mappings of a tree with different area-de... |

17 |
On optimal linear arrangements of trees
- Chung
- 1984
(Show Context)
Citation Context ...hat minimizes the maximum cut-width. Both problems are NP-hard for the general graphs [21]. In 1979, Shiloach [18] gave an O(n 2.2 ) algorithm to solve the MINSUM problem for trees, and in 1984 Chung =-=[2]-=- improved it to O(n 1.58 ). For MINCUT problems, Lengauer [9] introduced a polynomial time algorithm for trees whose cost is within a factor of two of the optimal in 1982, andsYannakakis [23] gave an ... |

12 |
DOMINO: Deterministic placement improvement with hill-climbing capabilities
- Doll, Johannes, et al.
- 1991
(Show Context)
Citation Context ...-layout area. In Table II we present the results using a conventional flow and FPD-SiMPA. In the conventional flow, we use SIS to do a minimum delay technology mapping, followed by Gordian and Domino =-=[3]-=- for placement, TimberWolf for global routing and YACR [13] for detailed routing. In FPDSiMPA, we use tree clustering and initial mapping of each tree for block width estimation, followed by Bear-FP [... |

12 |
Upper and lower bounds on the complexity of the min-cut linear arrangement problem on trees
- Lengauer
- 1982
(Show Context)
Citation Context ...d for the general graphs [21]. In 1979, Shiloach [18] gave an O(n 2.2 ) algorithm to solve the MINSUM problem for trees, and in 1984 Chung [2] improved it to O(n 1.58 ). For MINCUT problems, Lengauer =-=[9]-=- introduced a polynomial time algorithm for trees whose cost is within a factor of two of the optimal in 1982, andsYannakakis [23] gave an O(nlogn) dynamic programming algorithm to find the optimal so... |

8 |
Logic synthesis for VLSI design,” Memorandum UCB
- Rudell
- 1989
(Show Context)
Citation Context ...tree sub-graphs and each tree subgraph is mapped using a dynamic programming algorithm which finds the minimum gate area mapping of the tree in polynomial time. This work was later extended by Rudell =-=[14]-=- to minimum delay technology mapping and by Touati et al. [19] to minimize area mapping under delay constraints. In [1], Chaudhary and Pedram presented a dynamic programming algorithm to construct the... |

7 | Bear-FP: A Robust Framework For Floorplanning
- Pedram, Kuh
- 1992
(Show Context)
Citation Context ...] for placement, TimberWolf for global routing and YACR [13] for detailed routing. In FPDSiMPA, we use tree clustering and initial mapping of each tree for block width estimation, followed by Bear-FP =-=[12]-=- which does floorplanning and global routing. Then we call SiMPA for each tree subject to the delay budgets generated in the floorplanning stage. Domino is used to eliminate overlaps while TimberWolf ... |

7 |
Logic extraction based on normalized netlengths
- Vaishnav, Pedram
- 1995
(Show Context)
Citation Context ...assume a constant load ahead (that, is the input capacitance of a 2-input NAND gate and the capacitance of a wire segment whose length is statistically estimated based on the fanout count of the node =-=[20]-=-). After a match is found, we update the delay of all fanins of this match to use the correct load information since the match is henceforth known and the fanins are already placed and mapped. This is... |

1 |
Optimal Algorithm for Simultaneous Technology Mapping and Linear Placement,” CENG
- Lou, Salek
- 1997
(Show Context)
Citation Context ...ement. The following counter example shows how this can happen. Example: Assume at one step of dynamic programming, when solving the problem of minimizing the total area of a † Proofs can be found in =-=[10]-=-. β h . W } c Figure 1. Total area calculation tree, there are two sub-problems, T1 and T2. For T1 one design S1, and for T2 two designs S2,1 and S2,2, have been found (Figure 2), and totalArea(S2,1) ... |