Abstract

This paper describes an analog-to-digital converter which combines multiple delta--sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta--sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta--sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M.A parallel delta--sigma A/D converter implementation composed of two, four, and eight second-order delta--sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta--sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit beh...

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