BibTeX
@MISC{Jacob97software-managedaddress,
author = {Bruce Jacob and Trevor Mudge},
title = {Software-Managed Address Translation},
year = {1997}
}
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Abstract
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that softwaremanaged address translation is just as efficient as hardware -managed address translation, and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms. 1 Introduction In many commercial architectures the hardware support for memory management is unnecessarily complicated, places constraints on the operating sys...
Keyphrases
software-managed address translation address translation sub-page protection hardware-defined mechanism fast clock high clock-rate powerpc implementation software-managed translation shared memory simple design short design cycle memory-management hardware sparse address space memory management design mach charge operating sys memory management hardware support
