## BiCMOS Circuits for Analog Viterbi Decoders (1998)

Venue: | IEEE Trans. Circuits Syst. II |

Citations: | 14 - 2 self |

### BibTeX

@ARTICLE{Shakiba98bicmoscircuits,

author = {Mohammad Hossein Shakiba and David A. Johns and Senior Member and Kenneth W. Martin},

title = {BiCMOS Circuits for Analog Viterbi Decoders},

journal = {IEEE Trans. Circuits Syst. II},

year = {1998},

volume = {45},

pages = {1527--1537}

}

### Years of Citing Articles

### OpenURL

### Abstract

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

### Citations

1177 |
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
- Viterbi
- 1967
(Show Context)
Citation Context ...aper. The Viterbi algorithm (VA) [3] provides a practical means for realizing a maximum-likelihood sequence detection (MLSD) scheme. This technique was first proposed for decoding convolutional codes =-=[4]-=- and was later extended to the problem of optimum detection of digital sequences experiencing linear ISI [5], [6]. The basic idea is to consider the received sequence as a finite-state discrete-time M... |

749 | The Viterbi Algorithm
- Forney
- 1973
(Show Context)
Citation Context ...r group of symbols. Partialresponse signaling (PRS) [2] falls in this category. Sequence detection of partial-response signals receives most of our attention in this paper. The Viterbi algorithm (VA) =-=[3]-=- provides a practical means for realizing a maximum-likelihood sequence detection (MLSD) scheme. This technique was first proposed for decoding convolutional codes [4] and was later extended to the pr... |

326 | Analog Integrated Circuit Design - Johns, Martin - 1997 |

272 |
Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference
- Forney
- 1972
(Show Context)
Citation Context ...tion (MLSD) scheme. This technique was first proposed for decoding convolutional codes [4] and was later extended to the problem of optimum detection of digital sequences experiencing linear ISI [5], =-=[6]-=-. The basic idea is to consider the received sequence as a finite-state discrete-time Markov process contaminated by memoryless noise. A trellis diagram Manuscript received October 31, 1996; revised J... |

212 | Digital Communication
- Lee, Messerschmitt
- 1994
(Show Context)
Citation Context ...ODUCTION IN ESTIMATING a digital sequence, it is well known that if one received symbol contains information about other symbols, symbol-by-symbol detection will no longer lead to optimum performance =-=[1]-=-. This degradation arises when the symbol-by-symbol detector removes the effects of the other symbols in the detection process, hence, ignoring some useful information. For example, consider transmitt... |

28 |
A class of partial response systems for increasing storage density in magnetic recording
- Thapar, Patel
- 1987
(Show Context)
Citation Context ...on of the path-memory length. B. Binary EPR4 It has been shown that at high densities a class of EPR schemes can be utilized to resemble the spectrum of the read signal in a magnetic recording system =-=[23]-=-. Consequently, much effort has been directed toward an efficient implementation of their sequence detectors. EPR4, an EPR scheme withsSHAKIBA et al.: BICMOS CIRCUITS FOR ANALOG VITERBI DECODERS 1535 ... |

16 |
Partial-response signaling
- Kabal, Pasupathy
- 1975
(Show Context)
Citation Context ...rence contains information about the transmitted symbols, for optimum performance, the whole received sequence should be used to detect any symbol or group of symbols. Partialresponse signaling (PRS) =-=[2]-=- falls in this category. Sequence detection of partial-response signals receives most of our attention in this paper. The Viterbi algorithm (VA) [3] provides a practical means for realizing a maximum-... |

11 | An integrated analog CMOS Viterbi detector for digital magnetic recording - Mathews, Spencer - 1993 |

10 |
Correlative level coding and maximum-likelihood decoding
- Kobayashi
- 1971
(Show Context)
Citation Context ...detection (MLSD) scheme. This technique was first proposed for decoding convolutional codes [4] and was later extended to the problem of optimum detection of digital sequences experiencing linear ISI =-=[5]-=-, [6]. The basic idea is to consider the received sequence as a finite-state discrete-time Markov process contaminated by memoryless noise. A trellis diagram Manuscript received October 31, 1996; revi... |

8 |
A quaternary partial-response class-IV transceiver for 125 Mbit/s data transmission over unshielded twisted-pair cables: Principles of operation and VLSI realization
- Cherubini, Olcer, et al.
- 1995
(Show Context)
Citation Context ...to a quaternary dicode partial-response Viterbi decoder appears to be a likely candidate. Quaternary PRS has recently been proposed for high-rate data transmission over unshielded twisted-pair cables =-=[18]-=-. Also, due to its regularity, the implementation approach is well suited for automated design of analog Viterbi decoders. The analog-automation tool, which can extend down to layout [19], enables the... |

6 |
The Viterbi Algorithm Applied to Digital Data Transmission
- Hayes
- 2002
(Show Context)
Citation Context ...ated based on the error criterion. For a squareEuclidean criterion, these metrics are of the quadratic form, but, can be reduced to linear combinations of the received sample and some constant values =-=[20]-=-. The idea is to expand the quadratic terms and cancel out the common terms, which are not required during the ACS operations. Also, a fixed gain might be considered for all of the branches in the tre... |

4 |
Analog Viterbi decoding for high speed digital satellite channels
- Acampora, Gilmore
- 1978
(Show Context)
Citation Context ...wer constraints have motivated researchers to look at analog realizations of the algorithm as well. Analog Viterbi decoders have demonstrated size and power advantages over their digital counterparts =-=[8]–[-=-14] and many of today’s state-of-the-art partial-response maximum-likelihood read channels employ an analog Viterbi decoder in their processor core. In present partial-response class-IV systems, the... |

3 |
Memory management in a Viterbi algorithm
- Rader
- 1981
(Show Context)
Citation Context ...In addition to state metrics, enough knowledge regarding the paths along which these optimum metrics have been obtained should also be saved. A block of memory, used with different management methods =-=[7]-=-, can be utilized to save the required information. This information, stored in the form of digital sequences, enables the decoder to trace back the optimum paths ending on each state. Following the l... |

3 | et al., “A 72Mb/S PRML disk-drive channel chip with an analog sampled-data signal processor - Yamasaki - 1994 |

3 |
Diode-configured Viterbi algorithm error correcting decoder for convolutional codes
- Davis
(Show Context)
Citation Context ...detectors with increased numbers of states. Extended PRS Viterbi decoders are one example of such detectors. Generalizing other analog solutions is not feasible in practice. The technique proposed in =-=[15] i-=-s limited to a hards1528 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 12, DECEMBER 1998 decision detection. An extension to soft detection results... |

3 |
et al., "BALLISTIC: An Analog Layout Language
- Owen
- 1995
(Show Context)
Citation Context ...-pair cables [18]. Also, due to its regularity, the implementation approach is well suited for automated design of analog Viterbi decoders. The analog-automation tool, which can extend down to layout =-=[19]-=-, enables the analog design to be easily transferred from one technology to another. II. GENERAL OVERVIEW In an algorithmic realization of an MLSD, the metric assigned to each state of the trellis is ... |

2 | Analog implementation of class-IV partial-response Viterbi detector - Shakiba, Johns, et al. - 1994 |

1 | A 100Mbps optical transmission experiment employing a Viterbi decoder composed of analog circuits - Suzuki, Saitoh - 1989 |

1 | integrated analog CMOS Viterbi detector for digital magnetic recording - “An - 1993 |

1 |
200 MHz 3.3 V BiCMOS class-IV partial-response analog Viterbi decoder
- “A
- 1995
(Show Context)
Citation Context ...constraints have motivated researchers to look at analog realizations of the algorithm as well. Analog Viterbi decoders have demonstrated size and power advantages over their digital counterparts [8]�=-=��[14] a-=-nd many of today’s state-of-the-art partial-response maximum-likelihood read channels employ an analog Viterbi decoder in their processor core. In present partial-response class-IV systems, the powe... |

1 |
Decoder for implementing an approximation of the Viterbi algorithm using analog processing techniques
- Acampora
- 1978
(Show Context)
Citation Context ...ed in decoders with deep path memories. It is also likely to be slow, since it requires a diode-configured circuit with many diodes in cascade to settle at each time step. The technique introduced in =-=[16]-=- can be generalized, but, with an unnecessary growth in the number of analog building blocks. This results in a size and power inefficient circuit realization. The approach described here exploits the... |

1 |
General approach to implementing analogue Viterbi decoders
- Shakiba, Johns, et al.
(Show Context)
Citation Context ...perform the required functions in the Viterbi decoder. Simplicity is considered a basic requirement since speed, size, and power consumption are the major concerns. The original idea was published in =-=[17]-=-, however, with few circuit-level descriptions and analysis and no experimental results. This paper begins with a general overview of the approach, followed by details of a circuit-level implementatio... |

1 |
et al., “VLSI architectures for metric normalization in the Viterbi algorithm
- Shung
- 1990
(Show Context)
Citation Context ...diode. (a) Employing a mirror transistor. (b) Directing the collector current. range in internal calculations, several methods for normalizing the state metrics have been proposed in digital decoders =-=[21]-=-. Taking an average over the state metrics and setting it in each iteration to a desired value minimizes the required dynamic range. This optimum solution, costly for a digital realization, works well... |