A Dual-V_DD Low Power FPGA Architecture (2004)
| Venue: | IN PROCEEDINGS OF INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS |
| Citations: | 16 - 3 self |
BibTeX
@INPROCEEDINGS{Gayasen04adual-v_dd,
author = {A. Gayasen and K. Lee and N. Vijaykrishnan and M. Kandemir and M. J. Irwin and T. Tuan},
title = {A Dual-V_DD Low Power FPGA Architecture},
booktitle = {IN PROCEEDINGS OF INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS},
year = {2004},
pages = {145--157},
publisher = {}
}
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Abstract
The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. We evaluate the e#ectiveness of different VDD assignment algorithms and architectural implementations. Our
