Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits (2003)
| Citations: | 37 - 5 self |
BibTeX
@MISC{Jess03statisticaltiming,
author = {J. A. G. Jess and K. Kalafala and S. R. Naidu and R. H. J. M. Otten and C. Visweswariah},
title = {Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits},
year = {2003}
}
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Abstract
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the -42660 static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by 39516 's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and V dd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.
