Abstract

Network link emulation constitutes an important part of network emulation, wherein links in the topology are emulated to subject the network tra#c to di#erent bandwidths, latencies, packet loss distributions, and queuing models. Increasingly, experimenters are creating topologies with substantial emulation bandwidths; contributed both by a large number of low-speed links and a small number of high-speed links. It is a significant challenge for a link emulator to meet this requirement in real time. Existing solutions for link emulation use general-purpose PC-class machines; the well-understood hardware and software PC platform make it attractive for quick implementation and easy deployment. A PC architecture is largely optimized for compute bound applications with large amounts of exploitable instruction-level parallelism (ILP) and good memory reference locality. Networking applications, on the other hand, have little ILP and instead exhibit a coarser packet-level parallelism. In this thesis, we propose using network processors for building high capacity link emulators. Network processors are programmable processors that employ a multithreaded, multiprocessor architecture to exploit packet-level parallelism, and have instruction sets and hardware support geared towards e#cient implementation of common networking tasks. To evaluate our proposal, we have designed and implemented a link emulator, LinkEM, on the IXP1200 network processor. We present the design and a mapping of LinkEM's tasks across the multiple microengines and hardware threads of the IXP1200. We also give a detailed evaluation of LinkEM, which includes validating its emulation accuracy, and measuring its emulation throughput and link multiplexing capacity. Our evaluation shows that LinkEM has a factor of be...

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