BibTeX
@MISC{Banks_designof,
author = {David Banks},
title = {Design of a Synthesisable Reed-Solomon},
year = {}
}
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Abstract
error correction, verilog, synthesis, synthesisable, hardware, ECC, Galois field In this report we describe the design of a Reed-Solomon error correction core that supports errors and erasures decoding. In a second report HPL-2001-125 we describe the verification of this core. The core consists of separate encoder and decoder blocks that can be operated independently, each with symbol wide data paths. These blocks have sufficient throughput to handle back-to-back codewords, and the overall latency is typically less than two codewords. The design is expressed in the Verilog hardware description language (Verilog HDL), and is fully synthesisable. The design supports a wide
