## Performance Analysis and Optimization of Asynchronous Circuits (1991)

Citations: | 136 - 7 self |

### BibTeX

@TECHREPORT{Burns91performanceanalysis,

author = {Steven M. Burns and Alain J. Martin},

title = {Performance Analysis and Optimization of Asynchronous Circuits},

institution = {},

year = {1991}

}

### Years of Citing Articles

### OpenURL

### Abstract

We present a method for analyzing the time performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits---including those produced by using our synthesis method---these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization. 1 Introduction Performance analysis of a synchronous computer system is simplified by an external clock that partitions the events in the system into discrete segments. In a...

### Citations

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274 |
Combinatorial Optimization: Networks and
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- 1976
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Minimization Methods for Nondifferentiable Functions, in
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165 |
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- 1985
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Citation Context ...vel, the component delays are functions of transistor widths and, as such, the cycle period can be optimized with respect to these widths. Non-linear optimization methods (such as those used in TILOS =-=[3]-=- and COP [7]) can 2 be used to perform the optimization of this expression for the cycle period. Our approach differs from those used for synchronous systems because we optimize all critical paths sim... |

155 |
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
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Citation Context ...to synthesize the asynchronous systems. Furthermore, we use our formalism to model the performance of asynchronous circuits, and provide a method for optimizing such circuits for performance. Martin (=-=[9]-=- and elsewhere) has developed a synthesis method whereby asynchronous circuits are produced from concurrent program descriptions. By applying a systematic series of semantics-preserving transformation... |

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- 1980
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Citation Context ...and applies especially to repetitive computations. Early work in the scheduling of concurrent computing elements [14] is closely related to our approach. Previous work in the area of timed Petri nets =-=[13, 6]-=- applies to this problem as well. The results we describe here are based on event-rule systems, a different formalism that is more closely connected to the methods we use to synthesize the asynchronou... |

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Scheduling Parallel Computations
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- 1968
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Citation Context ...rk for determining the time needed to perform computations using asynchronous systems, and applies especially to repetitive computations. Early work in the scheduling of concurrent computing elements =-=[14]-=- is closely related to our approach. Previous work in the area of timed Petri nets [13, 6] applies to this problem as well. The results we describe here are based on event-rule systems, a different fo... |

81 |
The design of an asynchronous microprocessor
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Citation Context ...rcuits, these choices must be directed by performance concerns. We observed this potential benefit of performance-directed transformations during the design of the Caltech Asynchronous Microprocessor =-=[8]-=-. The decisions of what transformation to apply were based on performance goals and this accounts for its high performance. Event-rule (ER) systems can be used at each stage of the synthesis procedure... |

54 |
Synthesis of Asynchronous VLSI Circuits
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- 1993
(Show Context)
Citation Context ...od. Three stages of a four-phase lazy-active/passive (lap) FIFO (Example 2.4) with the datapath between the stages are shown in Figure 1. For a circuit level implementation of a lap stage, see [1] or =-=[10]-=-. The three critical cycles through the transitions of the middle process are represented by bold arcs in the collapsed-constraint graphs (Figure 2). Assuming all delays in the circuit are small compa... |

42 |
A Switch-Level Timing Verifier for Digital MOS VLSI
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Citation Context ...ence, Santa Cruz, CA, March 1991 1 is available in asynchronous systems. Analysis procedures must deal directly with cyclic critical paths; thus, existing critical-path analysis tools such as CRYSTAL =-=[11]-=- cannot be easily applied to this problem. This paper discusses a framework for determining the time needed to perform computations using asynchronous systems, and applies especially to repetitive com... |

24 | Syntax-directed translation of concurrent programs into self-timed circuits - Burns, Martin - 1988 |

16 |
Methods of Mathematical Economics
- Franklin
- 2002
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Citation Context ...o signify constraint (8). 2.3 Minimum-Period Linear Timing Functions Among the possible linear timing functions, there are those that minimize the cycle period p. The techniques of linear programming =-=[4]-=- can be used to find such a minimum-period linear timing function. 6 The constraints of a linear timing function, (8), are simple linear inequalities in the x v 's and p. By ordering the sets E 0 and ... |

15 |
Performance evaluation of concurrent systems using petri nets
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Citation Context ...and applies especially to repetitive computations. Early work in the scheduling of concurrent computing elements [14] is closely related to our approach. Previous work in the area of timed Petri nets =-=[13, 6]-=- applies to this problem as well. The results we describe here are based on event-rule systems, a different formalism that is more closely connected to the methods we use to synthesize the asynchronou... |

1 |
and Abbas El Gamal. Optimal selection of transistor sizes in digital VLSI circuits
- Marple
- 1987
(Show Context)
Citation Context ...ponent delays are functions of transistor widths and, as such, the cycle period can be optimized with respect to these widths. Non-linear optimization methods (such as those used in TILOS [3] and COP =-=[7]-=-) can 2 be used to perform the optimization of this expression for the cycle period. Our approach differs from those used for synchronous systems because we optimize all critical paths simultaneously.... |