## Algorithms for Performance Driven Design of Integrated Circuits (1996)

Citations: | 7 - 2 self |

### BibTeX

@TECHREPORT{Lillis96algorithmsfor,

author = {John Patrick Lillis},

title = {Algorithms for Performance Driven Design of Integrated Circuits},

institution = {},

year = {1996}

}

### OpenURL

### Abstract

### Citations

11488 |
Computers and Intractability: A Guide to the Theory of NP-Completeness
- Garey, Johnson
- 1979
(Show Context)
Citation Context ...ponent of the complexity, we assume the capacitive parameters of the problem are given as or translated into polynomially-bounded integers. As such, these algorithms have pseudo-polynomial complexity =-=[14]-=-. However, in these cases, the bounds are very pessimistic versus observed behavior. When signal slew is incorporated into the delay model, we are not able to give polynomial bounds due to degenerate ... |

9049 | Introduction to Algorithms
- Cormen, Leiserson, et al.
- 1990
(Show Context)
Citation Context ...urrence (Equation 3.1) and the sum of the edge weights matches the sum in the recurrence. By Lemma 3.3.2 we can compute D v (i; j) for all i; j by the Floyd-Warshall all-pairs shortest paths algorithm=-=[9]-=-. Since the Floyd-Warshall algorithm runs in O(n 3 ) time and is applied at each of the internal nodes of the tree, we have the following. Lemma 3.3.3 Problem 3.3.2 is solved in O(n 4 ) time by the ab... |

402 |
The transient response of damped linear networks with particular regard to wideband amplifiers
- Elmore
- 1948
(Show Context)
Citation Context ...els For a given routing tree possibly containing buffers, delay along a root-sink path is made of (1) delay along wires and (2) delay through buffers and the driving gate. This work adopts the Elmore =-=[13]-=- delay model for wires and considers two buffer delay models: a common RC model and an augmented model which considers signal slew. The capacitance c e and resistance r e of wire segment e having widt... |

370 |
The Steiner Tree Problem
- Hwang, Richards, et al.
- 1992
(Show Context)
Citation Context ...awn through the terminals (n = jN j). The grid formed by this set of points leads to a useful graph-theoretic formulation of the problem based on the the Grid Graph of N . Definition 3.2.1 Grid Graph =-=[21]-=-: Given a set of terminals N , N's Grid Graph GG(N) = (V; E) is defined by the following process: 44 Construct vertical and horizontal lines through each terminal. Let V be identified with the set of ... |

197 | Signal Delay in RC Tree Networks
- Rubinstein, Penfield, et al.
- 1983
(Show Context)
Citation Context ... of the rest of the routing tree) which are useful in the design of dynamic programming algorithms for timing optimization. For completeness, it should be noted that Rubinstein, Penfield and Horowitz =-=[37]-=- devised a sink independent upper bound model (RPH) based on Elmore delay. Letting r d;v be the total path resistance from the driver (including the driver), the RPH bound is given as X v2T r d;v (c(T... |

157 |
Introduction to algorithms: A creative approach
- Manber
- 1989
(Show Context)
Citation Context ...um (and the related Knapsack problem) have not been shown to be strongly NP-hard; in fact, pseudo-polynomial [14] dynamic programming algorithms have been devised for these problems (see, for example =-=[34]) and such-=- an algorithm can be used directly to solve Formulation 4.2.2. This can be seen by noticing that once s (and s crit ) are known, the "capacitance budgets" for S 1 and S 2 are described by th... |

144 |
On steiner’s problem with rectilinear distance
- Hanan
- 1966
(Show Context)
Citation Context ... u = 0 8u, the max source to sink delay is \Gammaq(T ). 3.2.2 Graphs, Trees and Permutations One of the classical results in the theory of Rectilinear Steiner Minimum Trees (RSMTs) is Hanan's theorem =-=[17]-=- which states that there always exists a RSMT for a terminal set N where all Steiner points are drawn from the n 2 points formed by the intersection of horizontal and vertical lines drawn through the ... |

118 | Optimal wire sizing and buffer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995 |

106 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...on technique of logic replication. Before presenting our results in logic replication, it is instructive to consider the traditional role of gate sizing in the typical design flow. Gate sizing (e.g., =-=[39]-=-) have proven to be an effective post-synthesis, circuit-level optimization technique. A circuit can be optimized by carefully sizing the gates to minimize a cost function (e.g., area) subject to a gi... |

104 |
On Steiner minimal trees with rectilinear distance
- Hwang
- 1976
(Show Context)
Citation Context ... we can prove that an algorithm for constructing a permutation ensures consistency with the MST, we guarantee that the min area solution induced bysis no worse than 3 2 times the optimal Steiner tree =-=[22]-=- while only relying on the MST indirectly in constructing the final topology. We present an algorithm for constructing permutations consistent with a given topology T such as the MST in the next secti... |

97 | A new class of iterative Steiner tree heuristics with good performance
- Kahng, Robins
- 1992
(Show Context)
Citation Context ...from the given topology. By utilizing this technique with the Minimum Spanning Tree as the given topology we approach the solution quality of the Batched 1-Steiner (B1S) algorithm of Kahng and Robins =-=[26]-=- which has reported among the best results in the literature. When using the result of Batched 1-Steiner as the given topology, we are able to improve routing area by 0:38% on average for 20-pin nets,... |

82 |
CMOS circuit speed and buffer optimization
- HEDENSTIERNA, JEPPSON
- 1987
(Show Context)
Citation Context ...rve is of practical significance as it provides added flexibility to the designer. The incorporation of signal slew is also significant since its contribution to total delay can be over 50% (see e.g. =-=[18]-=-) and therefore cannot be neglected in practice. The ability to use inverters as buffers rather than resorting to pairs of inverters to ensure proper signal polarity is also of practical utility. The ... |

82 |
On optimal interconnections for VLSI
- Kahng, Robins
- 1995
(Show Context)
Citation Context ...y segments on the p n boundary rows (columns) need be considered. 2 This is by no means a new observation (in fact, it can be shown that O(l p n) is the expected length of the MST -- see Chapter 5 of =-=[25]-=- for related information). Since the RMST is within a constant factor of the RSMT, it follows that the topology produced by P-TreeA is O(l p n) in length. 62 From this analysis (and assumption 2), we ... |

80 |
The Steiner Problem in Graphs
- Dreyfus, Wagner
- 1972
(Show Context)
Citation Context ...costs" S(v; i; j) and S b (v; i; j) are scalars giving the area of the optimal solution. The min area version of the algorithm can be thought of as a special case of the Dreyfus-Wagner (DW) algor=-=ithm [12]-=- for the Graph Steiner Problem. The DW algorithm uses a similar decomposition into sub-solutions; the difference is that instead of terminal subsets being determined by consecutive subsequences of a p... |

69 | Performance-driven interconnect design based on distributed RC delay model
- Cong, Leung, et al.
- 1993
(Show Context)
Citation Context ...o longer rely on this strong correlation between total wire length and performance and thus, various forms of the performance driven routing problem have recently received attention (e.g., [36], [3], =-=[6]-=- and [20]). While the advent of deep submicron technology has changed the objectives of classical problems in physical layout, it has also introduced new physical design problems. For instance, the te... |

54 | Near-optimal critical sink routing tree constructions
- Boese, Kahng, et al.
- 1995
(Show Context)
Citation Context ...bmicron range (0:5m and below), transistor switching speeds become proportionally faster, but wire resistance increases significantly. Consider the technology parameters in Table 3.1 (data taken from =-=[2]-=-; 2:0 and 1:2 micron data is from MOSIS and 0:5 micron data is from MCNC) 1 Of particular interest is the so-called resistance ratio; this figure represents the length of a wire with resistance equal ... |

54 | Simultaneous driver and wire sizing for performance and power optimization
- CONG, KOH, et al.
- 1994
(Show Context)
Citation Context ...his delay model is discussed in Section 2.6. 2.1.3 Previous Work in Wire Sizing Early work in wire sizing includes the work of Cong, Leung, Zhou and Koh who provided several studies of wire sizing in =-=[6, 7, 8]-=- and demonstrated its potential in improving delay. The first of these works [6] attacked the problem of minimizing delay under the Rubinstein, Penfield, Horowitz sink oblivious model discussed in Sec... |

50 | RC interconnect optimization under the Elmore delay model
- Sapatnekar
- 1994
(Show Context)
Citation Context .... al. also attacked the problem of incorporating a cost function such as area or power. Their formulation is, again, a weighted sum of their stated timing objective function and the cost function. In =-=[40]-=-, Sapatnekar studied the more common metric of maximum sourceto -sink delay -- or, more generally, the task of minimizing cost subject to given timing constraints (under the Elmore model). He noted th... |

45 |
Performance-driven placement of cell-based ic’s
- Jackson, Kuh
- 1989
(Show Context)
Citation Context ...ce register to register delays are so strongly affected by geometric distance -- i.e., wiring delay. Accordingly, a number of researchers have attacked the performance driven placement problem (e.g., =-=[24]-=-, [44], [11] and [43]). A similar situation holds in the case of routing. In the past, minimization of total routing wire length achieved multiple goals simultaneously; because delay was dominated by ... |

45 |
RITUAL: A performance driven placement algorithm
- Srinivasan, Chaudhary, et al.
- 1992
(Show Context)
Citation Context ...ister to register delays are so strongly affected by geometric distance -- i.e., wiring delay. Accordingly, a number of researchers have attacked the performance driven placement problem (e.g., [24], =-=[44]-=-, [11] and [43]). A similar situation holds in the case of routing. In the past, minimization of total routing wire length achieved multiple goals simultaneously; because delay was dominated by gate d... |

43 | Closing the gap: Nearoptimal steiner trees in polynomial time
- Griffith, Robins, et al.
- 1994
(Show Context)
Citation Context ...e 67 cost of O(n 5 ) run time versus O(n 3 ) for B1S). While the 0:38% average improvement appears quite small it is interesting when put in the context of the results reported by Griffith et. al. in =-=[15]-=-. In that paper, it was reported that for 20 pin nets, the optimal solution (derived through a branch-and-bound procedure) improved upon the Batched 1-Steiner solution by only about 0:46% (this can be... |

42 | A Methodology and Algorithms for Post-Placement Delay Optimization
- Kannan, Suaris, et al.
- 1994
(Show Context)
Citation Context ...ing buffer. Thus we denote the augmented delay equation as buf delay slew (b; c l ) = buf delay(b; c l ) +sb D Lprev : (2:2) This and similar models have been proposed in various contexts (e.g., [45],=-=[27]-=-). An extension of our algorithms to accommodate this delay model is discussed in Section 2.6. 2.1.3 Previous Work in Wire Sizing Early work in wire sizing includes the work of Cong, Leung, Zhou and K... |

38 | High-Performance Routing Trees with Identified Critical Sinks
- Boese, Kahng, et al.
- 1993
(Show Context)
Citation Context ...can no longer rely on this strong correlation between total wire length and performance and thus, various forms of the performance driven routing problem have recently received attention (e.g., [36], =-=[3]-=-, [6] and [20]). While the advent of deep submicron technology has changed the objectives of classical problems in physical layout, it has also introduced new physical design problems. For instance, t... |

35 |
The Fanout Problem: From Theory to Practice
- Berman, Carter, et al.
- 1989
(Show Context)
Citation Context ...mming algorithm. However, power considerations were not explicitly taken into account. 2.1.4 Previous Work in Buffer Insertion Research on buffer insertion includes the early works of Berman et. al., =-=[1]-=-, Touati [46], van Ginneken [48] and Dhar [10]. Other contributions in this area include [32], [42], [30], [27], and [47]. Much previous work (e.g., [46], [42], [1]) approach buffer insertion as a log... |

35 | Fidelity and near-optimality of Elmore-based routing constructions - Boese, Kahng, et al. - 1993 |

32 |
A Timing-Driven Global Router for Custom Chip Design
- Prasitjutrakul, Kubitz
- 1990
(Show Context)
Citation Context ...y, we can no longer rely on this strong correlation between total wire length and performance and thus, various forms of the performance driven routing problem have recently received attention (e.g., =-=[36]-=-, [3], [6] and [20]). While the advent of deep submicron technology has changed the objectives of classical problems in physical layout, it has also introduced new physical design problems. For instan... |

32 |
A heuristic algorithm for the fanout problem
- Singh, Sangiovanni-Vincentelli
- 1990
(Show Context)
Citation Context ...nd wiring delay; its effectiveness in logic optimization is well studied and many logic synthesis tools perform automatic buffer insertion (typically under the name fanout optimization -- e.g., [46], =-=[42]-=-). However, when interconnect delay is significant, it makes better engineering sense to approach buffer insertion as a physical layout problem; additionally, routability concerns favor a post-synthes... |

28 |
Optimal wiresizing under Elmore delay model
- Cong, Leung
- 1995
(Show Context)
Citation Context ...his delay model is discussed in Section 2.6. 2.1.3 Previous Work in Wire Sizing Early work in wire sizing includes the work of Cong, Leung, Zhou and Koh who provided several studies of wire sizing in =-=[6, 7, 8]-=- and demonstrated its potential in improving delay. The first of these works [6] attacked the problem of minimizing delay under the Rubinstein, Penfield, Horowitz sink oblivious model discussed in Sec... |

28 |
Simultaneous routing and buffer insertion for high performance interconnect
- Lillis, Cheng, et al.
- 1996
(Show Context)
Citation Context ...work presented here and some important open problems. First, it should be noted that the buffer insertion techniques of Chapter 2 can be integrated with the topology synthesis techniques of Chapter 3 =-=[31]. The-=- complexity of this simultaneous optimization is higher than either of the seperate techniques, but remains polynomial. As noted at the end of Chapter 3, there are a number of natural "P-Tree lik... |

27 |
A Performance-Driven Steiner Tree Algorithm Us lobal Ro 6(3
- Hong
(Show Context)
Citation Context ... rely on this strong correlation between total wire length and performance and thus, various forms of the performance driven routing problem have recently received attention (e.g., [36], [3], [6] and =-=[20]-=-). While the advent of deep submicron technology has changed the objectives of classical problems in physical layout, it has also introduced new physical design problems. For instance, the technique o... |

27 |
Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay
- van
- 1990
(Show Context)
Citation Context ... considerations were not explicitly taken into account. 2.1.4 Previous Work in Buffer Insertion Research on buffer insertion includes the early works of Berman et. al., [1], Touati [46], van Ginneken =-=[48]-=- and Dhar [10]. Other contributions in this area include [32], [42], [30], [27], and [47]. Much previous work (e.g., [46], [42], [1]) approach buffer insertion as a logic synthesis problem; in other w... |

26 | TimingDriven Routing for Building Block Layout - Jackson, Kuh, et al. - 1987 |

24 | Rectilinear Steiner Trees with minimum Elmore delay
- Boese, Kahng, et al.
- 1994
(Show Context)
Citation Context ...t into the nature of performance driven routing. The classical result of Hanan tells us that only points on the "Hanan Grid" need be considered as candidate Steiner points to achieve minimum=-= area. In [5]-=- Boese et. al. showned that Hanan's theorem does not hold when minimizing maximum source-to-sink Elmore delays -- sometimes the optimal placement of Steiner nodes is not on the Hanan Grid. However, th... |

20 | Coping with RC(L) interconnect design headaches
- Pileggi
- 1995
(Show Context)
Citation Context ... provides an excellent balance between ease of computation and accuracy. In fact it has been said to be the most accurate model which is an algebraic combination of the R's and C's of a circuit model =-=[35]-=-. Further, the model has been shown to have very good fidelity [2]; while the Elmore delay exhibits significant error versus Spice computed delay, an optimal solution under the Elmore model is typical... |

20 |
Adaptive Timing-Driven Layout for High Speed VLSI
- Sutanthavibul, Shragowitz
- 1990
(Show Context)
Citation Context ...er delays are so strongly affected by geometric distance -- i.e., wiring delay. Accordingly, a number of researchers have attacked the performance driven placement problem (e.g., [24], [44], [11] and =-=[43]-=-). A similar situation holds in the case of routing. In the past, minimization of total routing wire length achieved multiple goals simultaneously; because delay was dominated by gate delay, minimizin... |

18 |
A Replication Cut for Two-Way Partitioning
- Liu
- 1995
(Show Context)
Citation Context ...y synthesis. We also point out that work needs to be done to determine the effectiveness of gate replication in practice. Motivated by the impressive results in circuit partitioning using replication =-=[33]-=-, we also note that gate or block replication has potential beyond timing optimzation; in particular, routability can conceivably be improved by careful replication. Both the theoretical and practical... |

16 |
Optimal and Efficient Buffer Insertion and Wire Sizing
- Lillis, Cheng, et al.
- 1995
(Show Context)
Citation Context ...paper Sapatnekar proposed a convex programming formulation of the maximum delay, continuous wire-sizing problem followed by a sensitivity based mapping heuristic to discretize the solution. Later, in =-=[30]-=-, a dynamic programming algorithm which exploited the fact that the lengths of wire segments are discrete in nature (i.e., that they are integer multiples of a basic grid length) was given. This led t... |

15 |
Routability-Driven Fanout Optimization
- Vaishnav, Pedram
- 1993
(Show Context)
Citation Context ...ertion Research on buffer insertion includes the early works of Berman et. al., [1], Touati [46], van Ginneken [48] and Dhar [10]. Other contributions in this area include [32], [42], [30], [27], and =-=[47]-=-. Much previous work (e.g., [46], [42], [1]) approach buffer insertion as a logic synthesis problem; in other words, buffer trees are imposed on the network prior to physical layout. There are importa... |

13 |
Minimal delay interconnect design using alphabetic trees
- Vittal, Marek-Sadowska
- 1994
(Show Context)
Citation Context ...asymmetric loads (and in fact does not take technological parameters into account at all). Nevertheless, the routing trees it produces are often of high quality. The work of Vittal and Marek-Sadowska =-=[49]-=- used the abstraction of Alphabetic Trees to heuristically construct routing trees. Their reported results are comparable to those of SERT in both delay and area. Previous work in static topology wire... |

12 | Dynamically-wiresized elmore-based routing constructions
- Hodes, McCoy, et al.
- 1994
(Show Context)
Citation Context ...river itself. The practical utility of such topologies is unclear since the routing area they consume is so high and the congestion near the driver may be intolerable. The later work of Hodes et. al. =-=[19]-=- had some success in reducing this tendency of SERT by incorporating the notion of wire sizing to drive the construction. Other performance driven routing work includes the A-Tree algorithm of Cong et... |

8 |
A Fast and Efficient Algorithm for Determining Fanout Trees
- Lin, Marek-Sadowska
- 1991
(Show Context)
Citation Context ... Previous Work in Buffer Insertion Research on buffer insertion includes the early works of Berman et. al., [1], Touati [46], van Ginneken [48] and Dhar [10]. Other contributions in this area include =-=[32]-=-, [42], [30], [27], and [47]. Much previous work (e.g., [46], [42], [1]) approach buffer insertion as a logic synthesis problem; in other words, buffer trees are imposed on the network prior to physic... |

7 | Timing driven placement using complete path delays - Donath, Norman, et al. - 1990 |

4 |
Strongly np-hard discrete gate sizing problems
- Li
- 1993
(Show Context)
Citation Context ...onable delay models by convex optimization techniques [39]. On the other hand, the discrete gate sizing problem where each gate has a finite library of implementations has been shown to be NP-complete=-=[28]-=-. 75 76 We propose that gate replication techniques can be applied after the gate sizing phase to further optimize the circuit timing and area (alternatively, iterating sizing and replication phases i... |

3 | A Unified Theory for Mixed CMOS/BiCMOS Buffer Optimization - Sakurai - 1992 |

2 |
Delay Optimization Algorithms For Tree Models of MOS Circuits
- Dhar
- 1987
(Show Context)
Citation Context ...s were not explicitly taken into account. 2.1.4 Previous Work in Buffer Insertion Research on buffer insertion includes the early works of Berman et. al., [1], Touati [46], van Ginneken [48] and Dhar =-=[10]-=-. Other contributions in this area include [32], [42], [30], [27], and [47]. Much previous work (e.g., [46], [42], [1]) approach buffer insertion as a logic synthesis problem; in other words, buffer t... |

2 | Wiresizing and Buffer Sizing for Power-Delay Tradeoffs Using a Sensitivity Based Heuristic - Shah, Sapatnekar |

2 |
Performance-Oriented Technology Mapping," Ph.D dissertation, Memorandum No
- Touati
- 1990
(Show Context)
Citation Context ...elay and wiring delay; its effectiveness in logic optimization is well studied and many logic synthesis tools perform automatic buffer insertion (typically under the name fanout optimization -- e.g., =-=[46]-=-, [42]). However, when interconnect delay is significant, it makes better engineering sense to approach buffer insertion as a physical layout problem; additionally, routability concerns favor a post-s... |

1 |
The Elmore delay as a bound for RC trees with gerneralized input signals
- Gupta, Tutuianu, et al.
- 1995
(Show Context)
Citation Context ...ptimal solution under Spice computed delay. Two other features of the Elmore model make it an appealing optimization metric. First, it provide an absolute upper bound on the 50% delay for RC circuits =-=[16] (i.e., al-=-though it exhibits error, it is one-sided error). Second, it has certain "separability" properties (i.e., the delay associated with a subtree can be computed independently of the rest of the... |

1 |
Computational Geometry," Ch. 7
- Yao
- 1990
(Show Context)
Citation Context ...q) is suboptimal -- i.e., if the grey region in the figure contains any points. Such a datastructure solves a special case of the Orthogonal Range Query problem from Computational Geometry (see e.g., =-=[51]-=-). Our problem is a special case for two reasons: first we need not retrieve or count all (c 0 ; q 0 )'s satisfying the property and second, the subspace we are interested in is defined by two inequal... |