Abstract

In this paper we present a new model for diagnosis of errors in Synchronous Sequential Circuits (SCC) on the functional level. In contrast to many previously published approaches we do not consider a specific implementation. Instead we use tests based on the transition behavior of the corresponding Finite State Machine (FSM). Thus, the approach can be used for verification and test. We describe a method for constructing a minimal cost test based on AND/OR graphs. Exact and heuristic methods are presented. First experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Nowadays, circuit design is becoming more and more complex. Thus, the error probability also increases. Since time-to-market aspects are increasingly important it is desirable to detect errors as early as possible. Additionally, this also reduces the production costs. For this, nowadays CAD tools should also support features for error diagnosis, i.e. error...

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