Abstract

A design structure is presented to assist in the design of IEEE compliant floating point hardware. The basis of the process is an abstraction of the bitwise operations found in hardware to reals and integers. This simplifies the definition of functionality prior to going to hardware. The final design structure will include a set of general algorithms defined for floating point operations (add, sub, multiply, division, square root) which are verified with respect to the IEEE standard. The designer then instantiates the general algorithms to complete the algorithmic specification. The algorithms are then mapped to hardware, maintaining the abstraction. The result is a verified functional description of the hardware which can then be realized by conventional techniques or by refining the description to bitwise operations. This paper is a work in progress which describes the design process to get a functional description of the hardware. Current work has focused on subtractive division and...

Citations