The Alewife CMMU: Addressing the Multiprocessor Communications Gap (1994) [9 citations — 5 self]
http://www.cs.berkeley.edu/~kubitron/papers/alewif
http://www.cs.berkeley.edu/~kubitron/papers/alewif
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Abstract:
. Communications functionality of the A#1000 CMMU includes# # Support for distributed# cache#coherent shared memory via the LimitLESS cache#coherence protocol#3## the A#1000 supports up to #ve hardware pointers per memory line for normal data sharing and can invoke software interrupt handlers to employ additional pointers. Clean data can be fetched from a neighboring node in 30 cycles. # Support for fast user#level messaging with integrated DMA#4#. A simple message# consist# ing of a header and one data word# can be launched in seven cycles. # Several mechanisms for latency tolerance# including non#binding software prefetch and rapid context switching. A remote cache miss is signaled immediately to the Sparcle processor# which can switch to a new context in 14 cycles. # To appear in HOTCHIPS #94. 1 In addition# the A#1000 CMMU includes a number of features for support of a complete multiprocessor syste
Citations
| 183 | LimitLESS directories: a scalable cache coherence scheme – Chaiken, Kubiatowics, et al. - 1991 |
| 89 | Sparcle: An Evolutionary Processor Design for Multiprocessors – Agarwal, Kubiatowicz, et al. - 1993 |
| 53 | Anatomy of a message in the Alewife multiprocessor – Kubiatowicz, Agarwal - 1993 |
| 2 | Kubiatowicz� and Anant Agarwal. LimitLESS Directories� A Scalable Cache Coherence Scheme – John - 1990 |
| 2 | Sparcle: Today's Micro for Tomorrow's Multiprocessor – Agarwal, Babb, et al. - 1992 |
| 1 | Kubiatowicz� David Kranz� Beng�Hong Lim� Donald Yeung� Godfrey D�Souza� and Mike Parkin. Sparcle� An Evolutionary Processor Design for Multiprocessors – John - 1993 |

