On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits

On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits (1997)

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by Zahava Koren , Israel Koren

Venue:	IEEE TRANS. ON VLSI SYSTEMS
Citations:	2 - 2 self

BibTeX

@ARTICLE{Koren97onthe,
    author = {Zahava Koren and Israel Koren},
    title = {On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits},
    journal = {IEEE TRANS. ON VLSI SYSTEMS},
    year = {1997},
    volume = {5},
    number = {5},
    pages = {3--14}
}

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Abstract

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the oorplan can affect the projected yield. We study several general oorplan structures, make some specic recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a non-negligible way, for chips with or without fault-tolerance.

Citations

12	Dobberpuhl et al., “A 200-MHz 64-b dual-issue CMOS microprocessor - W - 1992
11	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays - Singh - 1988
10	Yield Models for Defect Tolerant VLSI circuits: A Review - Koren, Strapper - 1989
6	A Statistical Study of Defect Maps of Large Area VLSI ICs - Koren, Koren, et al. - 1994
6	private communication - Shifman, Yung
5	A Unified Negative Binomial Distribution for Yield Analysis of Defect Tolerant Circuits - Koren, Koren, et al. - 1993
4	Modeling defect spatial distribution - Meyer, Pradhan - 1989
3	Dobberpuhl et al., "A 200-MHz 64-b dual-issue CMOS microprocessor - W - 1992
3	et al., "A Yield Enhancement Methodology for Custom VLSI - Collica - 1992
2	Does the Floorplan of a Chip Affect Its Yield - Koren, Koren - 1993
2	et al., \A Yield Enhancement Methodology for Custom VLSI - Collica - 1992
1	The Impact of Floorplanning on the Yield of Large Area ICs - Koren, Koren - 1995
1	Jouppi et al., "A 300-MHz 115-W 32-b Bipolar ECL Microprocessor - P - 1993
1	et al., "An 80-MFLOPs (Peak) 64-b Microprocessor for Parallel Computer - Nakano - 1992
1	et al., "A Wafer-Scale-Level System Integrated LSI Containing Eleven 4-Mb DRAMs, six 64-Kb SRAMs, and an 18K-Gate Array - Sato - 1992
1	Private communication - Collica
1	Little et al., "Redundancy for Yield Enhancement in the 3D Computer - Yung, M - 1989
1	Does the Floorplan of a Chip Aect Its Yield - Koren, Koren - 1993
1	Jouppi et al., \A 300-MHz 115-W 32-b Bipolar ECL Microprocessor - P - 1993
1	et al., \An 80-MFLOPs (Peak) 64-b Microprocessor for Parallel Computer - Nakano - 1992
1	et al., \A Wafer-Scale-Level System Integrated LSI Containing Eleven 4-Mb DRAMs, six 64-Kb SRAMs, and an 18K-Gate Array - Sato - 1992
1	Little et al., \Redundancy for Yield Enhancement in the 3D Computer - Yung, M - 1989
1	Interstitial Redundancy: An Area Ecient Fault Tolerance Scheme for Larger Area VLSI Processor Array - Singh - 1988