Abstract

In this paper, three demands of a good logic simulator for hierarchical circuits are postulated: stack oriented signal assignment, hierarchical circuit representation and linear runtime. It is shown that the intuitive idea of a hierarchical simulator does not hold condition 3 having a runtime of \Theta(n²) in the circuit size. May this be improved or is there a contradiction in these conditions? Not in the way that there are two conflicting groups, as for each pair of these conditions an algorithm may be presented. But it is shown that there is no way to fulfill all of them at once!

Citations