Automatic Synthesis of Regular Architectures Optimized at the Bit Level (1997)
BibTeX
@MISC{Dinechin97automaticsynthesis,
author = {Florent De Dinechin and Patricia le Moënner},
title = {Automatic Synthesis of Regular Architectures Optimized at the Bit Level},
year = {1997}
}
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Abstract
: This paper presents methods based on the formalism of affine recurrence equations for the synthesis of bit-level regular architectures from word-level (integer or real) algorithms. Because of bit-level dependency analysis, the arrays have optimal efficiency. We present two possible design flows leading to architectures based either on bit-parallel or bit-serial operators. The first one is fully automated. Key-words: high level synthesis, regular arrays, arithmetic operators (R'esum'e : tsvp) Also published in the Proceedings of the Workshop on Design Methodologies for Signal Processing -- Zakopane, Poland -- 29-30 August 1996 * This research is partly supported by CNET/France Telecom. ** ffdupontg,flemoenneg@irisa.fr CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE Centre National de la Recherche Scientifique Institut National de Recherche en Informatique (URA 227) Universit e de Rennes 1 -- Insa de Rennes et en Automatique -- unit e de recherche de Rennes Synth`ese automatique...
