## Automatic Synthesis of Regular Architectures Optimized at the Bit Level (1997)

### BibTeX

@MISC{Dinechin97automaticsynthesis,

author = {Florent De Dinechin and Patricia le Moënner},

title = {Automatic Synthesis of Regular Architectures Optimized at the Bit Level},

year = {1997}

}

### OpenURL

### Abstract

: This paper presents methods based on the formalism of affine recurrence equations for the synthesis of bit-level regular architectures from word-level (integer or real) algorithms. Because of bit-level dependency analysis, the arrays have optimal efficiency. We present two possible design flows leading to architectures based either on bit-parallel or bit-serial operators. The first one is fully automated. Key-words: high level synthesis, regular arrays, arithmetic operators (R'esum'e : tsvp) Also published in the Proceedings of the Workshop on Design Methodologies for Signal Processing -- Zakopane, Poland -- 29-30 August 1996 * This research is partly supported by CNET/France Telecom. ** ffdupontg,flemoenneg@irisa.fr CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE Centre National de la Recherche Scientifique Institut National de Recherche en Informatique (URA 227) Universit e de Rennes 1 -- Insa de Rennes et en Automatique -- unit e de recherche de Rennes Synth`ese automatique...

### Citations

216 | Some efficient solutions to the affine scheduling problem: I. onedimensional time
- Feautrier
- 1992
(Show Context)
Citation Context ...Thus the bit-serial interpretation is inherently different from the usual systolic interpretation of an Alpha program, for it involves the interpretation of several indices as a multidimensional time =-=[4]-=-. Therefore, the description of a bit-serial array in Alpha is not trivial, and is not automated so far. First of all, the operators synthesized previously described one computation. We need to expres... |

161 |
The organization of computations for uniform recurrence equations
- Karp, Miller, et al.
- 1967
(Show Context)
Citation Context ... flows leading to architectures based either on bit-parallel or bit-serial operators. The first one is fully automated. 1. INTRODUCTION The formalism of Systems of Affine Recurrence Equations (SAREs) =-=[5]-=- is widely used for the design of regular parallel hardware for real-time signal-processing applications. It allows the stepwise refinement of an algorithm, from a very high level functional specifica... |

80 |
Systolic arrays (for VLSI
- Kung, Leiserson
(Show Context)
Citation Context ... Abstract Array Serializing and scheduling the real matrixvector product yields a SARE whose core is given as Prog.5, which represents a classic systolic array (Fig.6) similar to Kung and Leisersons’ =-=[6]-=- but with unidirectional data-flow. In this figure, the V[1] V[2] V[3] M[1,1] M[1,2] M[1,3] p=1 p=N - M[2,1] M[2,2] M[2,3] - - M[3,1] M[3,2] M[3,3] Figure 6. Real-typed systolic array for the matrix-v... |

44 |
Synthesizing systolic arrays from Recurrences Equations with Linear Dependencies
- Rajopadhye, Purushothaman, et al.
- 1986
(Show Context)
Citation Context ...o [8] for a detailed description of the synthesis flow. A program like that of Prog.2 is first analyzed (type-checked) to ensure the consistency of the domains and expressions. Then it is uniformized =-=[13, 15]-=- to remove the data broadcasts and non-local communications. It is then scheduled, i.e. each computation of the program is assigned an affine time function consistent with the data dependencies [1]. F... |

33 |
The alpha language and its use for the design of systolic arrays
- Verge, Mauras, et al.
- 1991
(Show Context)
Citation Context ...a very high level functional specification, down to a range of implementation-level descriptions suitable for simulation, compilation to sequential or parallel code, or hardware synthesis [10]. Alpha =-=[8]-=- is a strongly typed functional language based on the SARE formalism. The MmAlpha environment provides a set of automatic and semi-automatic tools to manipulate Alpha programs. These tools are formall... |

32 |
Two‟s complement pipelined multipliers
- Lyon
- 1976
(Show Context)
Citation Context ... output by the last (W-1-th) processor at time b+2W-1. The complete program describes a virtual linear array (Fig.2) composed of elementary cells similar to the first W − 1 cells of Lyon’s multiplier =-=[9]-=-. Additional program transformations will lead to a program which may be interpreted as lowlevel hardware, expressed in a subset of Alpha called AlpHard[7] which has the following characteristics: • h... |

32 |
On the analysis and synthesis of VLSI algorithms
- Moldovan
- 1982
(Show Context)
Citation Context ...rithm, from a very high level functional specification, down to a range of implementation-level descriptions suitable for simulation, compilation to sequential or parallel code, or hardware synthesis =-=[10]-=-. Alpha [8] is a strongly typed functional language based on the SARE formalism. The MmAlpha environment provides a set of automatic and semi-automatic tools to manipulate Alpha programs. These tools ... |

15 | The ALPHA language
- Wilde
- 1994
(Show Context)
Citation Context ...NT 2.1. The Language We introduce here the main features of the language with the help of Prog.1, a simple Alpha program which describes a classical binary adder. The interested reader is referred to =-=[14, 2]-=- for an extensive description of the language in its current version. Alpha variables (here A, B, S, X, C) denote data arrays defined over a domain which is a con-Program 1 Binary addition in Alpha 1... |

12 | Derivation of data parallel code from a functional program
- Quinton, Rajopadhye, et al.
- 1995
(Show Context)
Citation Context ...n environment which allows us to derive implementation-level descriptions from high-level Alpha programs. We focus here on hardware synthesis, although imperative code [12] and data-parallel programs =-=[11]-=- may also be generated. The reader is referred to [8] for a detailed description of the synthesis flow. A program like that of Prog.2 is first analyzed (type-checked) to ensure the consistency of the ... |

11 | Scheduling uniform loop nests
- Darte, Robert
- 1992
(Show Context)
Citation Context ...3, 15] to remove the data broadcasts and non-local communications. It is then scheduled, i.e. each computation of the program is assigned an affine time function consistent with the data dependencies =-=[1]-=-. Finally an affine change of basis is performed on the index space of each variable, so that one of the indices represents the time at which this variable is computed, and the other indices specify t... |

7 | The naive execution of affine recurrence equations
- Rajopadhye, Wilde
- 1995
(Show Context)
Citation Context ...tica-based program transformation environment which allows us to derive implementation-level descriptions from high-level Alpha programs. We focus here on hardware synthesis, although imperative code =-=[12]-=- and data-parallel programs [11] may also be generated. The reader is referred to [8] for a detailed description of the synthesis flow. A program like that of Prog.2 is first analyzed (type-checked) t... |

7 | Converting affine recurrence equations to quasi-uniform recurrence equations
- Yaacoby, Cappello
- 1988
(Show Context)
Citation Context ...o [8] for a detailed description of the synthesis flow. A program like that of Prog.2 is first analyzed (type-checked) to ensure the consistency of the domains and expressions. Then it is uniformized =-=[13, 15]-=- to remove the data broadcasts and non-local communications. It is then scheduled, i.e. each computation of the program is assigned an affine time function consistent with the data dependencies [1]. F... |

5 | Designing systolic arrays with DIASTOL - Frison, Gachet, et al. - 1986 |

3 |
Tanguy Risset. Structuration of the alpha language
- Dinechin, Quinton
- 1995
(Show Context)
Citation Context ...o manipulate Alpha programs. These tools are formally proven to preserve the semantics of the specification. One strong point of Alpha is the possibility of organizing SAREs into hierarchical modules =-=[2]-=-. So far these modules have been used at the top of the design flow (for the structured specification and analysis of algorithms), and at the bottom (to express hierarchical hardware designs). This pa... |

2 |
Sanjay Rajopadhye, Tanguy Risset, and Patrice Quinton. Generating regular arithmetic circuits with alphard
- Moenner, Perraudeau
- 1996
(Show Context)
Citation Context ...o the first W − 1 cells of Lyon’s multiplier [9]. Additional program transformations will lead to a program which may be interpreted as lowlevel hardware, expressed in a subset of Alpha called AlpHard=-=[7]-=- which has the following characteristics: • hierarchical structuring (because design process is itself hierarchical); • genericity (to allow for reuse of components); • regularity. AlpHard is organize... |

1 | An introduction to bit-serial architectures for vlsi signal processing - Denyer - 1983 |