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Adaptive Cache Bypassing for Inclusive Last Level Caches
| Citations: | 2 - 0 self |
BibTeX
@MISC{Gupta_adaptivecache,
author = {Saurabh Gupta and Hongliang Gao and Huiyang Zhou},
title = {Adaptive Cache Bypassing for Inclusive Last Level Caches},
year = {}
}
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Abstract
Abstract — Cache hierarchy designs, including bypassing, replacement, and the inclusion property, have significant performance impact. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the last level cache (LLC) performance. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion property. This paper presents a solution to enabling cache bypassing for inclusive caches. We introduce a bypass buffer to an LLC. Bypassed cache lines skip the LLC while their tags are stored in this bypass buffer. When a tag is evicted from the bypass buffer, it invalidates the corresponding cache lines in upper level caches to ensure the inclusion property. Our key insight is that the lifetime of a bypassed line, assuming a well-designed bypassing algorithm, should be short in upper level caches and is most likely dead when its tag is evicted from the bypass buffer. Therefore, a small bypass buffer is sufficient to maintain the inclusion property and to reap most performance benefits of bypassing. Furthermore, the bypass buffer facilitates bypassing algorithms by providing the usage information of bypassed lines. We show that a top performing cache bypassing algorithm, which is originally designed for non-inclusive caches, performs comparably for inclusive caches equipped with our bypass buffer. The usage information collected from the bypass buffer also significantly reduces the cost of hardware implementation compared to the original design.
Keyphrases
bypass buffer inclusion property adaptive cache bypassing inclusive last level cache inclusive cache cache bypassing upper level cache bypassed line usage information original design non-inclusive cache small bypass buffer last level cache performance benefit effective technique significant performance impact well-designed bypassing algorithm recent work inclusive cache hierarchy cannot benefit top performing cache cache line high performance cache hardware implementation key insight corresponding cache line abstract cache hierarchy design
