## Energy minimization using multiple supply voltages (1996)

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Venue: | In International Symposium on Low Power Electronics and Design |

Citations: | 132 - 5 self |

### BibTeX

@INPROCEEDINGS{Chang96energyminimization,

author = {Jui-ming Chang and Massoud Pedram},

title = {Energy minimization using multiple supply voltages},

booktitle = {In International Symposium on Low Power Electronics and Design},

year = {1996},

pages = {157--162}

}

### Years of Citing Articles

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### Abstract

Abstract|We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both non-pipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a supply voltage level (selected from a xed and known number of voltage levels) to each operation in a data ow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using three supply voltage levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single supply voltage level.

### Citations

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Citation Context ...ase integer delay values on any path) by Tmax . Clearly, Tmax is bounded from above by an integer M . Let j I j = n where n is the number of nodes in the DFG. The MV S problem \Pi is a number problem =-=[12]-=- because there exists no polynomial p such that M is less than or equal to p(n). This implies that we can develop an algorithm for solving \Pi with a pseudo-polynomial time complexity (\Pi is not NP -... |

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Citation Context ...r a simple DFG C. Module sharing after scheduling Our goal is to minimize the resources after the scheduling has been done. The problem can be formulated as a minimal coloring of a circular arc graph =-=[17]-=-. (For a functionally pipelined data-path, a row in the resource allocation table is a track which is circular in nature, i.e. the Lth c-step in the current frame comes before the first c-step of next... |

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Citation Context ...gnment. If the assumptions made in [6] do not hold for a given problem instance, then their proposed algorithm will produce a suboptimal solution without any performance guarantee. Usami and Horowitz =-=[7]-=- proposed a technique to reduce the energy consumption in a circuit by making use of two supply voltage levels. The idea is to operate gates on the critical paths at the higher voltage level and the g... |

113 | A Monte Carlo approach for power estimation
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Citation Context ...apacitance of the functional unit FU i , and ff FU is the average switching activity at the inputs of FU i . C i is calculated for each functional unit using circuit or gate level simulation [Deng94] =-=[BuNa93]-=- and curve fitting. Obviously C i depends on the module type, input data width, technology and logic style used and internal module structure. Equation ( 1) is the basis of many macromodeling techniqu... |

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Citation Context ... level shifters per pipeline initiation, we are indeed minimizing the average power dissipation. An algorithm for performing scheduling and allocation for functionally pipelined DFG's is described in =-=[16]-=-. This technique known as the feasible scheduling deals with single cycle operations and operations that can be chained together in one c-step, but not multi-cycle or multi-frame operations. B. Handli... |

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Citation Context ...thors use dynamic programming to cover a subject graph by a library of pattern graphs with the goal of minimizing area/power while satisfying given timing constraints. The MV S problem was tackled in =-=[6]-=- where the authors proposed an algorithm for minimizing the energy consumption of a non-pipelined design while meeting the computation time constraint. The authors assume that delay vs. supply voltage... |

70 |
Hyperlp: A system for power minimization using architectural transformations
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Citation Context ...he circuit. The most effective way to reduce power consumption is to lower the supply voltage level for a circuit. Reducing the supply voltage however increases the circuit delay. Chandraskan et. al. =-=[ChPo92]-=- compensate for the increased delay by shortening critical paths in the data-path using This research was supported in part by SRC under contract no. 94DJ -559 and ARPA under contract no. F33615-95-C-... |

64 | Behavioral level power estimation and exploration
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Citation Context ...th, technology and logic style used and internal module structure. Equation ( 1) is the basis of many macromodeling techniques for energy estimation and has been used in the works of [PoCh91][SvLi94] =-=[MeRa94]-=-. Power estimation accuracies of 10-15% have been reported for this model (A more accurate power macro-model is presented in [LaRa94].). To be more precise, we present some results for the set of data... |

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Citation Context ...nal arrival timesfi is NP-complete. We will show (cf. Section IV) that the MV S problem for minimum energy is also NP-complete. Another similar problem is that of delay constrained technology mapping =-=[3]-=- [4] [5]. Our method for solving multiple voltage scheduling is similar to the method used in [4] [5]. In these works, the authors use dynamic programming to cover a subject graph by a library of patt... |

44 |
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Citation Context ...nergy models. More precisely, any energy macro-model whose parameters depend on the input and/or output activity factors can be used here. This includes for example, the power macro-model reported in =-=[10]-=-. We assume that the dynamic energy dissipation in a functional unit is given by this equation: EFU i = F i (ff i;1 ; ff i;2 ) \Delta V 2 i (1) where V i is the supply voltage of functional unit FU i ... |

43 |
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Citation Context ... at the higher voltage level and the gates on the non-critical path at the lower voltage level. In this manner, the energy consumption is minimized without affecting the circuit speed. Power Profiler =-=[8]-=- primarily uses a genetic search algorithmsto solve the multiple voltage scheduling problem. Johnson and Roy presented an ILP based formulation for the multiple voltage scheduling problem for non-pipe... |

31 |
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Citation Context ...erformed our new methods on various benchmarks including aTest DFG, AR Filter, Elliptical Wave Filter[GeEl92], Discrete Cosine Transform, Robotic Arm Controller, 2nd-order Adaptive Transversal Filter =-=[Hayk91]-=- and Di erential Equation Solver [CaWo91]. Our experimental results are shown in Table 4. E 1 and E 4 are the average energy obtained when libraries contain modules running at f5V g and f5V ,3:3V ,2:4... |

30 |
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Citation Context ... whereby the energy value of a multiple fanout point is divided by its fanout count when its is propagated upward in the DFG. This heuristic is also adopted in technology mapping programs such as MIS =-=[13]-=- or ad-mapper [4] and tends to produce good results. General DFG's contain conditional branches. We use nodes D and J to indicate the distribute and join nodes in order to express the conditional bran... |

26 | On the circuit implementation problem
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Citation Context ...arks are provided in Sections VI and VII. II. Related Problems The Multiple-voltage scheduling problem (MV S) as described above is closely related to the circuit implementation problem as defined in =-=[2]-=-. The latter problem is to minimize the total gate area in a circuit by selecting a gate IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATTION (VLSI) SYSTEMS, VOL. 5, NO. 4, DECEMBER 1997 2 implementatio... |

26 | Power efficient technology decomposition and mapping under an extended power consumption model
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Citation Context ...val timesfi is NP-complete. We will show (cf. Section IV) that the MV S problem for minimum energy is also NP-complete. Another similar problem is that of delay constrained technology mapping [3] [4] =-=[5]-=-. Our method for solving multiple voltage scheduling is similar to the method used in [4] [5]. In these works, the authors use dynamic programming to cover a subject graph by a library of pattern grap... |

24 |
Low power register allocation and binding
- CHANG, PEDRAM
- 1995
(Show Context)
Citation Context ...mpatible operations. This algorithm uses conventional techniques to detect operation compatibility and mutual exclusiveness of operations (as in parallel branches). We use a scheme similar to that of =-=[14]-=- for minimum energy module binding using a max-cost network flow algorithm. Details can be found in [15]. V. Functionally Pipelined Data-path A. Background In a functionally pipelined design, several ... |

24 |
Power analysis for CMOS/BiCMOS circuits
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(Show Context)
Citation Context ...hysical capacitance of the functional unit FU i , and ff FU is the average switching activity at the inputs of FU i . C i is calculated for each functional unit using circuit or gate level simulation =-=[Deng94]-=- [BuNa93] and curve fitting. Obviously C i depends on the module type, input data width, technology and logic style used and internal module structure. Equation ( 1) is the basis of many macromodeling... |

20 |
Architectural Synthesis and Optimization of Digital Systems
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Citation Context ...cation table is a track which is circular in nature, i.e. the Lth c-step in the current frame comes before the first c-step of next frame). The exact solution is obtained by the algorithm proposed in =-=[18]-=- which solves the register allocation problem in cyclic data flow graphs by using a multi-commodity flow formulation. Instead, we have adopted a less expensive heuristic for doing module sharing as de... |

19 |
A model for estimating power dissipation in a class of DSP VLSI chips
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Citation Context ...e, input data width, technology and logic style used and internal module structure. Equation ( 1) is the basis of many macromodeling techniques for energy estimation and has been used in the works of =-=[PoCh91]-=-[SvLi94] [MeRa94]. Power estimation accuracies of 10-15% have been reported for this model (A more accurate power macro-model is presented in [LaRa94].). To be more precise, we present some results fo... |

18 | Computing the area versus delay trade-off curves in technology mapping
- Chaudhary, Pedram
- 1995
(Show Context)
Citation Context ...arrival timesfi is NP-complete. We will show (cf. Section IV) that the MV S problem for minimum energy is also NP-complete. Another similar problem is that of delay constrained technology mapping [3] =-=[4]-=- [5]. Our method for solving multiple voltage scheduling is similar to the method used in [4] [5]. In these works, the authors use dynamic programming to cover a subject graph by a library of pattern ... |

14 |
Optimal VLSI Architectural Synthesis
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(Show Context)
Citation Context ...al Results We use the module library with voltage, energy, and delay as specified in Table 3. We performed our new methods on various benchmarks including a Test DFG, AR Filter, Elliptical Wave Filter=-=[GeEl92]-=-, Discrete Cosine Transform, Robotic Arm Controller, 2nd-order Adaptive Transversal Filter [Hayk91] and Differential Equation Solver [CaWo91]. Our experimental results are shown in Table 4. E 1 and E ... |

9 |
A power estimation tool and prospects of power savings in CMOS VLSI chips
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- 1994
(Show Context)
Citation Context ... data width, technology and logic style used and internal module structure. Equation ( 1) is the basis of many macromodeling techniques for energy estimation and has been used in the works of [PoCh91]=-=[SvLi94]-=- [MeRa94]. Power estimation accuracies of 10-15% have been reported for this model (A more accurate power macro-model is presented in [LaRa94].). To be more precise, we present some results for the se... |

8 | Computers and Tractability: A Guide to the Theory of NP-Completeness - Garcy, Johnson - 1979 |

6 |
Computing the area versus delay trade-o curves in technology mapping
- Chaudhary, Pedram
- 1995
(Show Context)
Citation Context ...nal arrival time is NP-complete. We will show (cf. Section IV) that the MVS problem for minimum energy is also NP-complete. Another similar problem is that of delay constrained technology mapping [3] =-=[4]-=- [5]. Our method for solving multiple voltage scheduling is similar to the method used in [4] [5]. In these works, the authors use dynamic programming to cover a subject graph by a library of pattern ... |

4 |
Power e cient technology decomposition and mapping under an extended power consumption model
- Tsui, Pedram, et al.
- 1994
(Show Context)
Citation Context ...arrival time is NP-complete. We will show (cf. Section IV) that the MVS problem for minimum energy is also NP-complete. Another similar problem is that of delay constrained technology mapping [3] [4] =-=[5]-=-. Our method for solving multiple voltage scheduling is similar to the method used in [4] [5]. In these works, the authors use dynamic programming to cover a subject graph by a library of pattern grap... |

3 |
Low-Power data-path Scheduling under resource
- Johnson, Roy
- 1996
(Show Context)
Citation Context ...a genetic search algorithmsto solve the multiple voltage scheduling problem. Johnson and Roy presented an ILP based formulation for the multiple voltage scheduling problem for non-pipelined design in =-=[9]-=-. Both algorithms have exponential worst-case complexity and hence the results are suboptimal for large problem instances where computation time is bounded due to practical considerations. In addition... |

3 | A Monte Carlo approach for power estimation - Yang, Trick� - 1993 |

3 |
High-level VLSI synthesis”, PP. 256
- Camposanoand, Wolf
(Show Context)
Citation Context ...marks including aTest DFG, AR Filter, Elliptical Wave Filter[GeEl92], Discrete Cosine Transform, Robotic Arm Controller, 2nd-order Adaptive Transversal Filter [Hayk91] and Di erential Equation Solver =-=[CaWo91]-=-. Our experimental results are shown in Table 4. E 1 and E 4 are the average energy obtained when libraries contain modules running at f5V g and f5V ,3:3V ,2:4V ,1:5V g, respectively. Column correspon... |

3 |
Power Efcient Technology Decomposition and Mapping Under and Extended Power Consumption Model
- Tsui, Pedram, et al.
- 1994
(Show Context)
Citation Context .... Multiple-voltage scheduling problem for low power is therefore NP-hard (Proof is by restriction [GaJo79].). Another similar problem is that of delay constrained technology mapping [ToMo90] [ChPe92] =-=[TsPe94]-=-. Our method for solving multiple voltage scheduling is similar to the method used in delay constrained technology mapping [ChPe92] [TsPe94]. In these works, the authors try to cover a subject graph b... |

2 |
How to Minimize Energy Using Multiple Supply Voltages", CENG
- Chang, Pedram
- 1996
(Show Context)
Citation Context ...ing activity information). The delay function for successive module alternatives at the same node n are then merged by applying a lower-bound merge operation on the corresponding delay functions. See =-=[11]-=- for details of operations. The delay function addition and merging are performed recursively until the root of the tree is reached. The resulting function is saved in the tree at its corresponding no... |

2 |
High-level VLSI synthesis", PP. 256
- Camposanoand, Wolf
- 1991
(Show Context)
Citation Context ...rks including a Test DFG, AR Filter, Elliptical Wave Filter[GeEl92], Discrete Cosine Transform, Robotic Arm Controller, 2nd-order Adaptive Transversal Filter [Hayk91] and Differential Equation Solver =-=[CaWo91]-=-. Our experimental results are shown in Table 4. E 1 and E 4 are the average energy obtained when libraries contain modules running at f5V g and f5V , 3:3V , 2:4V , 1:5V g, respectively. Column corres... |

2 |
Adaptive Filter Theory", 2nd edition
- Haykin
- 1991
(Show Context)
Citation Context ...rformed our new methods on various benchmarks including a Test DFG, AR Filter, Elliptical Wave Filter[GeEl92], Discrete Cosine Transform, Robotic Arm Controller, 2nd-order Adaptive Transversal Filter =-=[Hayk91]-=- and Differential Equation Solver [CaWo91]. Our experimental results are shown in Table 4. E 1 and E 4 are the average energy obtained when libraries contain modules running at f5V g and f5V , 3:3V , ... |

2 |
R.W.Brodersen. HYPER-LP:A System for Power Minimization Using Architectural Transformations
- Chandrakasan, Potkonjak, et al.
- 1992
(Show Context)
Citation Context ...and systems. The most e ective way to reduce power consumption is to lower the supply voltage level for a circuit. Reducing the supply voltage however increases the circuit delay. Chandraskan et. al. =-=[1]-=- compensate for the increased delay by shortening critical paths in the data-path using behavioral transformations such as parallelization or pipelining The resulting circuit consumes lower average po... |

1 |
R.W.Brodersen, "HYPER-LP:A System for Power Minimization Using Architectural Transformations
- Chandrakasan, Potkonjak, et al.
- 1992
(Show Context)
Citation Context ...nd systems. The most effective way to reduce power consumption is to lower the supply voltage level for a circuit. Reducing the supply voltage however increases the circuit delay. Chandraskan et. al. =-=[1]-=- compensate for the increased delay by shortening critical paths in the data-path using behavioral transformations such as parallelization or pipelining The resulting circuit consumes lower average po... |

1 |
Power Efficient Register Assignment
- Chang, Pedram
- 1995
(Show Context)
Citation Context ...utual exclusiveness of operations (as in parallel branches). We use a scheme similar to that of [14] for minimum energy module binding using a max-cost network flow algorithm. Details can be found in =-=[15]-=-. V. Functionally Pipelined Data-path A. Background In a functionally pipelined design, several instances of the execution of a data flow graph are overlapped in time. The time domain is discretized i... |

1 | Golumbic� �Algorithmic Graph Theory and Perfect Graphs - �Golu80� - 1980 |

1 | Haykin� �Adaptive Filter Theory�� 2nd edition - �Hayk91� - 1991 |

1 | On The Circuit Implementation Problem - Agrawal, Sahni� - 1992 |

1 | Sarrafzadeh� �Variable Voltage Schedul� ing - M - 1991 |