Optimal Spilling for CISC Machines with Few Registers (2000) [48 citations — 1 self]
http://www.cs.princeton.edu/~appel/papers/spill.ps
http://www.cs.princeton.edu/~appel/papers/spill.pd
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author = {Andrew W. Appel and Lal George},
title = {Optimal Spilling for CISC Machines with Few Registers},
booktitle = {In Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation},
year = {2000},
pages = {243--253},
publisher = {ACM Press}
}
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Abstract:
Register allocation based on graph coloring performs poorly for machines with few registers, if each temporary is held either in machine registers or memory over its entire lifetime. With the exception of short-lived temporaries, most temporaries must spill -- including long lived temporaries that are used within inner loops. Liverange splitting before or during register allocation helps to alleviate the problem but prior techniques are sometimes complex, make no guarantees about subsequent colorability and thus require further iterations of splitting, pay no attention to addressing modes, and make no claim to optimality. We formulate the register allocation problem for CISC architectures with few registers in two parts: an integer linear program that determines the optimal location to break up the implementation of a live range between registers and memory, and a register assignment phase that we guarantee to complete without further spill code insertion. Our linear programming model ...
