Design and Implementation of the MorphoSys Reconfigurable Computing Processor (2000)
| Venue: | Journal of VLSI and Signal Processing-Systems for Signal, Image and Video Technology |
| Citations: | 12 - 0 self |
BibTeX
@INPROCEEDINGS{Lee00designand,
author = {Ming-hau Lee and Hartej Singh and Guangming Lu and Nader Bagherzadeh and Fadi J. Kurdahi and Fadi and J. Kurdahi},
title = {Design and Implementation of the MorphoSys Reconfigurable Computing Processor},
booktitle = {Journal of VLSI and Signal Processing-Systems for Signal, Image and Video Technology},
year = {2000},
publisher = {Kluwer Academic Publishers}
}
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Abstract
. In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 m, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance...
