An Accurate Worst Case Timing Analysis for RISC Processors (1995)
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| Venue: | IN IEEE REAL-TIME SYSTEMS SYMPOSIUM |
| Citations: | 94 - 3 self |
BibTeX
@INPROCEEDINGS{Lim95anaccurate,
author = {Sung-Soo Lim and Young Hyun Bae and Gyu Tae Jang and Byung-Do Rhee and Sang Lyul Min and Chang Yun Park and Heonshik Shin and Kunsoo Park and Soo-Mook Moon and Chong Sang Kim},
title = {An Accurate Worst Case Timing Analysis for RISC Processors},
booktitle = {IN IEEE REAL-TIME SYSTEMS SYMPOSIUM},
year = {1995},
pages = {97--108},
publisher = {}
}
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Abstract
An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning...
