Abstract

We present a recursive method for generating layout for VLSI chips which combines the flexibility of gate array and standard cell layout with the control and density of custom layout. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense VLSI microprocessor chips automatically. d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA ii Table of Contents 1. Introduction 1 2. The Annotated Hierarchical Netlist 1 2.1. Cell Generators 2 2.2. Netlist Traversal 5 3. Layout Generation 5 3.1. Hand-Drawn Cells 6 3.2. Leaf Cells 7 3.3. Composite Cells 8 3.4. Routing 9 3.5. Netlist Hierarchy Equals Layout Hierarchy? 10 4. Results 11 References 13 iii iv List of Figures ...

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