Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines (1989)
| Citations: | 192 - 13 self |
BibTeX
@MISC{Jouppi89availableinstruction-level,
author = {Norman P. Jouppi and Superscalar and Superpipelined Machines and David W. Wall},
title = {Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines},
year = {1989}
}
Years of Citing Articles
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
Superscalar machines can issue several instructions per cycle. Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit. In this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism. A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism for a series of benchmarks. Results of these simulations in the presence of various compiler optimizations are presented. The average degree of superpipelining metric is introduced. Our simulations suggest that this metric is already high for many machines. These machines already exploit all of the instruction-level parallelism available in many non-numeric applications, even without parallel instruction issue or higher degrees of pipelining. This is a preprint of a paper that will be presented at the 3rd International Conference on Architectur...
