## New Algorithms for Gate Sizing: A Comparative Study (1996)

Venue: | IN DAC |

Citations: | 34 - 1 self |

### BibTeX

@INPROCEEDINGS{Coudert96newalgorithms,

author = {Olivier Coudert and Ramsey Haddad and Srilatha Manne},

title = {New Algorithms for Gate Sizing: A Comparative Study},

booktitle = {IN DAC},

year = {1996},

pages = {734--739},

publisher = {}

}

### Years of Citing Articles

### OpenURL

### Abstract

Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, non-linear, non-unimodal, constrained optimization. The goal is to overcome the non-linearity and non-unimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.

### Citations

251 | A survey of power estimation techniques in VLSI circuits
- Najm
- 1994
(Show Context)
Citation Context ...erturbation functions, e.g., guarded randomization, (un)guarded sumof outputs' slacks maximization,but none of them were as good as maximizing TS(N). 3 An overview on power estimation can be found in =-=[16, 6]-=-. function PowerOptimize(N;S); DelayOptimize(N;S); if S(N ) < 0 then S = S S(N ); GoToLocalMin(N; [NEG(S); P ]; [NEG(S);Relax ]); Figure 5: Power optimization under delay constraints. or the best ... |

200 | Signal Delay in RC Tree Networks - Rubinstein, Penfield, et al. - 1983 |

194 |
TILOS: A Posynomial Programming Approach to Transistor Sizing
- Fishburn, Dunlop
- 1985
(Show Context)
Citation Context ...er optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in [20, 12]. Using a RC delay model, TILOS =-=[8]-=- expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation [23, 22]. Linear programming is used in [2]... |

111 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...[20, 12]. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation =-=[23, 22]-=-. Linear programming is used in [2] thanks to a piecewise linear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point me... |

108 | Engineering Optimization - Theory and Applications - Rao - 1998 |

49 |
Delay analysis of series-connected MOSFET circuits
- Sakurai, Newton
- 1991
(Show Context)
Citation Context ...te, the output load (the output capacitance seen at the output of the gate) and on the input transition time (the time needed by the input signal to achieve its transition). The reader is referred to =-=[1, 24, 18, 13, 21, 14]-=- for the presentation of some delay models. An extensive study of dierent input transition time sensitive delay models shows that a table lookup approach is more accurate than most of the multi-coec... |

42 |
Optimization-based transistor sizing
- Shyu, Fishburn, et al.
- 1988
(Show Context)
Citation Context ...[20, 12]. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation =-=[23, 22]-=-. Linear programming is used in [2] thanks to a piecewise linear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point me... |

21 | Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
- BORAH, OWENS, et al.
- 1995
(Show Context)
Citation Context ... method. Gate sizing is formulated as non-linear programming in [4, 11, 15] and solved with Lagrangian multipliers [19, pp. 60{74]. Analytical delay/power/area models or continuous sizing are used in =-=[20, 10, 22, 3]-=- to avoid facing the combinatorial explosion, or tosll the lack ofsrst and second derivatives. These approaches suer from some of the following problems. (1) The delay and power cost models are no lo... |

19 | Gate sizing: a general purpose optimization approach
- Coudert
(Show Context)
Citation Context ...exist. This paper addresses gate sizing as dened above. Section 2 discusses constraint free delay optimization. It describessve dierent algorithms: genetic, polytope, greedy, Hooke & Jeeves, and GS =-=[5]-=- (Global Sizing). Section 3 addresses power minimization under delay constraints. Experimental results of Section 4 will show that GS is the best of these approaches for delay optimization, and that i... |

16 |
Gate Sizing
- Berkelaar, Jess
- 1990
(Show Context)
Citation Context ...[8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation [23, 22]. Linear programming is used in =-=[2]-=- thanks to a piecewise linear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point method. Gate sizing is formulated as ... |

16 |
Transistor size optimization in the Tailor layout system
- Marple
- 1989
(Show Context)
Citation Context ...ear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point method. Gate sizing is formulated as non-linear programming in =-=[4, 11, 15]-=- and solved with Lagrangian multipliers [19, pp. 60{74]. Analytical delay/power/area models or continuous sizing are used in [20, 10, 22, 3] to avoid facing the combinatorial explosion, or tosll the l... |

14 |
Optimization of high-speed CMOS logic circuits with analytical models signal delay, chip area, and dynamic power dissipation
- Hoppe, Neuendorf, et al.
- 1990
(Show Context)
Citation Context ... method. Gate sizing is formulated as non-linear programming in [4, 11, 15] and solved with Lagrangian multipliers [19, pp. 60{74]. Analytical delay/power/area models or continuous sizing are used in =-=[20, 10, 22, 3]-=- to avoid facing the combinatorial explosion, or tosll the lack ofsrst and second derivatives. These approaches suer from some of the following problems. (1) The delay and power cost models are no lo... |

12 |
Advanced library characterization for high-performance asic
- Phelps
- 1991
(Show Context)
Citation Context ...te, the output load (the output capacitance seen at the output of the gate) and on the input transition time (the time needed by the input signal to achieve its transition). The reader is referred to =-=[1, 24, 18, 13, 21, 14]-=- for the presentation of some delay models. An extensive study of dierent input transition time sensitive delay models shows that a table lookup approach is more accurate than most of the multi-coec... |

11 |
LATTIS: An Iterative Speedup Heuristic for Mapped Logic
- Fishburn
- 1992
(Show Context)
Citation Context ...free delay optimization. Greedy algorithm is the most widely used method for gate sizing. It iteratively resizes nodes on or near the critical path (see below) of the network using various heuristics =-=[9, 23, 8, 3, 12]-=-. The goal of this paper is to explore new alternatives and show that a better optimization method evolves from these considerations. We have chosen four highly non-linear optimization oriented method... |

10 | Input waveform slope effect in CMOS delays - Auvergne, Azemard, et al. - 1990 |

9 |
Analytical Power/Timing Optimization Technique for Digital System
- Ruehli, Wolff, et al.
- 1977
(Show Context)
Citation Context ...y optimization and delay constrained power optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in =-=[20, 12]-=-. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation [23, 22]... |

8 |
AESOP: A Tool for Automated Transistor Sizing
- Hedlund
- 1987
(Show Context)
Citation Context ...ear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point method. Gate sizing is formulated as non-linear programming in =-=[4, 11, 15]-=- and solved with Lagrangian multipliers [19, pp. 60{74]. Analytical delay/power/area models or continuous sizing are used in [20, 10, 22, 3] to avoid facing the combinatorial explosion, or tosll the l... |

5 |
An Algorithm for CMOS Timing and Area Optimization
- Lee, Soukup
- 1984
(Show Context)
Citation Context ...y optimization and delay constrained power optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in =-=[20, 12]-=-. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to solve such a posynomial formulation [23, 22]... |

4 |
Transistor Sizing
- Cirit
- 1987
(Show Context)
Citation Context ...ear delay model. A convex programming formulation based on pseudo-posynomial is presented in [22], and is solved using an interior point method. Gate sizing is formulated as non-linear programming in =-=[4, 11, 15]-=- and solved with Lagrangian multipliers [19, pp. 60{74]. Analytical delay/power/area models or continuous sizing are used in [20, 10, 22, 3] to avoid facing the combinatorial explosion, or tosll the l... |

3 |
Automated Library Characterization and Timing Model Accuracy Issues when Interfacing to Different CAD
- Martinez
(Show Context)
Citation Context ...te, the output load (the output capacitance seen at the output of the gate) and on the input transition time (the time needed by the input signal to achieve its transition). The reader is referred to =-=[1, 24, 18, 13, 21, 14]-=- for the presentation of some delay models. An extensive study of dierent input transition time sensitive delay models shows that a table lookup approach is more accurate than most of the multi-coec... |

3 |
An Accurate Slope-Dependent Delay Model
- Zewi, Barkai, et al.
- 1990
(Show Context)
Citation Context |

1 | Analytical Power/Timing Optimization Technique for - Ruehli, Wolff, et al. - 1977 |

1 | Optimization-Based Transistor Sizing", in - Shyu, Sangiovanni-Vincentelli, et al. - 1988 |

1 |
Input Waveform Slope Eects in CMOS Delays
- Auvergne, Azemard, et al.
- 1990
(Show Context)
Citation Context |

1 | Optimization: Theory and Applications,Wiley Eastern Ld - Rao - 1978 |