Abstract

This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this application is discussed and a trade off to existing approaches is investigated. The design and analyzing task at this level is described in detail. As example a 1-bit full adder design in static CMOS is inspected with regard to power consumption and delay. In algorithmic scope both, single- and multi-objective optimization are regarded here. 1 Introduction Development of new concepts to low power design needs a comparison to existing alternatives. Independant of the abstract level an optimal decision in lower, as well as in upper levels is essential to determine the concepts potential. This paper focuses on the circuit level as a parameter adjustment task. Instead of commonly used local meliorating procedure evolutionary algorithms as a global optimum seeking method are used here. A global search could guide the designer to alternative designs far away from usual ones. This becomes m...

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