## Circuit Analysis and Design using Evolutionary Algorithms (2000)

Citations: | 2 - 0 self |

### BibTeX

@TECHREPORT{Thomas00circuitanalysis,

author = {Marc Thomas and Christian Burwick and Karl Goser},

title = {Circuit Analysis and Design using Evolutionary Algorithms},

institution = {},

year = {2000}

}

### OpenURL

### Abstract

This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this application is discussed and a trade off to existing approaches is investigated. The design and analyzing task at this level is described in detail. As example a 1-bit full adder design in static CMOS is inspected with regard to power consumption and delay. In algorithmic scope both, single- and multi-objective optimization are regarded here. 1 Introduction Development of new concepts to low power design needs a comparison to existing alternatives. Independant of the abstract level an optimal decision in lower, as well as in upper levels is essential to determine the concepts potential. This paper focuses on the circuit level as a parameter adjustment task. Instead of commonly used local meliorating procedure evolutionary algorithms as a global optimum seeking method are used here. A global search could guide the designer to alternative designs far away from usual ones. This becomes m...

### Citations

852 | Evolutionary Algorithms in Theory and Practice: Evolution Strategies, Evolutionary Programming, Genetic Algorithms - Bäck |

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(Show Context)
Citation Context ...imization algorithm is required which does not result in a single realization but gives an appropriate coverage of the Pareto set. An algorithm complying these requirements is the predator-prey model =-=[7]-=-. It is an evolutionary algorithm based on a structured population. Individuals (here: circuit parameter sets) correspond to the prey and are locally selected for replacement by different evaluation c... |

12 | Low power design in deep submicron electronics - Nebel, Mermet - 1997 |

9 |
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(Show Context)
Citation Context ...nt towards given goals step by step. This motivates multiple works to study automated design optimization at physical level. Several approaches to automated design optimization in circuit level exist =-=[1, 2, 3]-=-. They differ in their specification of the problem as well as in solving aspects. But all dispense from global optimality to comply computation time constraints for practical use. The problem specifi... |

4 |
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(Show Context)
Citation Context ...nt towards given goals step by step. This motivates multiple works to study automated design optimization at physical level. Several approaches to automated design optimization in circuit level exist =-=[1, 2, 3]-=-. They differ in their specification of the problem as well as in solving aspects. But all dispense from global optimality to comply computation time constraints for practical use. The problem specifi... |

4 |
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Citation Context ...e as some characteristics are left beside. First, analog behavior of the circuits becomes more important as the devices are shrink-ed to sub-m feature size, i.e. digital elements gain analog aspects [=-=4]-=-. This leads to more complicated models and an increased role to the different transistor operation areas which require numerical simulation. Additionally, the intention of robustness becomes more and... |

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(Show Context)
Citation Context ...approach used here is to set a constraint for each object except one. In manual design optimization, rough rules to achieve a low power consumption exist, like the two step design concept proposed in =-=[5]-=-. At first the circuit is designed to minimum delay and afterwards the supply voltage is reduced till delay-constraint is exploited. The result should be a low-voltage, low-power circuit design. Exper... |

3 |
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Citation Context ...er circuit design. Experiments show that this approach results in a significantly higher power consumption in relation to a full adjusted design. The 1-bit Full Adder As an example a 1-bit full adder =-=[6]-=- in static CMOS is used here. It consists of 28 transistors each adjustable in width and length. Involving supply voltage 57 parameters are free to choose. The signal levels are assumed to be equal to... |

2 |
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(Show Context)
Citation Context ...nt towards given goals step by step. This motivates multiple works to study automated design optimization at physical level. Several approaches to automated design optimization in circuit level exist =-=[1, 2, 3]-=-. They differ in their specification of the problem as well as in solving aspects. But all dispense from global optimality to comply computation time constraints for practical use. The problem specifi... |