A Correctness Model for Pipelined Microprocessors (0)
| Citations: | 18 - 1 self |
BibTeX
@INPROCEEDINGS{Windley_acorrectness,
author = {Phillip J. Windley and Michael L. Coe},
title = {A Correctness Model for Pipelined Microprocessors},
booktitle = {},
year = {},
pages = {33--51},
publisher = {Springer-Verlag}
}
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Abstract
What does it mean for an instruction pipeline to be correct? We recently completed the specification and verification of a pipelined microprocessor called Uinta. Our proof makes no simplifying assumptions about data and control hazards. This paper presents the specification, describes the verification, and discusses the effect of pipelining on the correctness model. 1 Introduction Much has been written over the years regarding the formal specification and verification of microprocessors. Most of these efforts have been directed at non--pipelined microprocessors [Gor83, Bow87, Hun87, CCLO88, Coh88, Joy88, Hun89, Win90, Her92, SWL93, Win94b]. The verification of pipelined microprocessors presents unique challenges. The correctness model is somewhat different than the standard correctness models used previously (see Section 7.1). Besides the correctness model, the concurrent operations inherent in a pipeline lead to hazards which must be considered in the proof. There are three typ...
