## Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation (1997)

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Venue: | In Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design |

Citations: | 90 - 8 self |

### BibTeX

@INPROCEEDINGS{Chen97fastand,

author = {Chung-ping Chen and Chris C. N. Chu and D. F. Wong},

title = {Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation},

booktitle = {In Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design},

year = {1997},

pages = {617--624}

}

### Years of Citing Articles

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### Abstract

This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g. minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and "one-gate/wire-at-a-time" local optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 13824 gates and wires in about 13 minutes using under 12 MB memory on an IBM RS/6000 workstation. 1 Introduction Since the invention of integrated circuits almost 40 years ago, gate si...

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Citation Context ...t width wire area capacitance and the wire fringing capacitance of segment , respectively. For , let and be, respectively, the lower bound and upper bound of the value of , i.e., . Elmore delay model =-=[11]-=- is used for delay calculation. Basically, the Elmore delay along a signal path is the sum of the delays associated with the resistors in the path, where the delay associated with a resistor is equal ... |

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Citation Context ...so a linear function of . In other words, the dynamic power can be handled in exactly the same way as the total component area. Sapatnekar and Chuang [21] showed that the short-circuit power of gates =-=[25]-=- can sometimes be a nonnegligible part ofsCHEN et al: SIMULTANEOUS GATE AND WIRE SIZING BY LAGRANGIAN RELAXATION 1023 the total power dissipation. We notice that our approach can also be extended to h... |

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Citation Context ...importance. In the past, gate delay was the dominant factor in determining circuit performance. Thus, gate and transistor sizing have been extensively studied in the literature [6], [12], [16], [17], =-=[23]-=-. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9], [19], [22]. Sin... |

86 |
An application oriented guide to Lagrangian relaxation
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Citation Context ...ian relaxation. Lagrangian relaxation is a general technique for solving constrained optimization problems. We outline the basic idea of Lagrangian relaxation below. More details can be found in [1], =-=[13], and [1-=-4]. In Lagrangian relaxation, “troublesome” constraints are “relaxed” and incorporated into the objective function after multiplying them by constants called Lagrange multipliers, one multipli... |

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Citation Context ...2], [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], =-=[9]-=-, [19], [22]. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous g... |

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Citation Context ... solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous gate and wire sizing have been reported [2], [7], =-=[8]-=-, [18], [20]. Chen et al. [2], Cong and Koh [8], Menezes et al. [18], and Menezes et al. [20] considered a single routing tree together Manuscript received July 22, 1998; revised November 24, 1998. Th... |

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Citation Context ...17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9], [19], =-=[22]-=-. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous gate and wire... |

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Citation Context ... For the purpose of delay calculation, we model components as resistance-capacitance (RC) circuits. If component is a gate (i.e., ), it is modeled as a switch-level RC circuit as shown in Fig. 3. See =-=[24]-=- for a reference of this model. Let be the gate size. Then the output resistance , ands1016 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 7, JULY 1999 Fig... |

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Citation Context ...tions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous gate and wire sizing have been reported [2], [7], [8], =-=[18]-=-, [20]. Chen et al. [2], Cong and Koh [8], Menezes et al. [18], and Menezes et al. [20] considered a single routing tree together Manuscript received July 22, 1998; revised November 24, 1998. This wor... |

29 |
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
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Citation Context ...erature [6], [12], [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years =-=[2]-=-, [4], [7], [9], [19], [22]. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on... |

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Citation Context ...re [6], [12], [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], =-=[4]-=-, [7], [9], [19], [22]. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simu... |

16 | An efficient approach to simultaneous transistor and interconnect sizing
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Citation Context ...], [12], [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], =-=[7]-=-, [9], [19], [22]. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultane... |

15 |
A Fast Algorithm for Optimal Wire-Sizing Under Elmore Delay Model
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(Show Context)
Citation Context ...optimally by a greedy algorithm based on iteratively resizing the gates and wire segments. A similar technique has been successfully applied to some other wire or buffer sizing problems before (e.g., =-=[3]-=- and [9]). Chu and Wong [5] proved that for wire sizing of interconnect trees, the greedy algorithm runs in time linear to the number of segments. If we resize component (i.e., changing ) while keepin... |

15 |
Geometric programming-theory and application
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Citation Context ... a PC with a 333-MHz Pentium II processor. We notice that the gate and wire sizing problem is similar to the transistor sizing problem. In this paper, our problem is formulated as a geometric program =-=[10]-=-. Fishburn and Dunlop [12] have shown a long time ago that the transistor sizing problem can also be formulated as a similar geometric program. However, it would be very slow to solve the geometric pr... |

15 | Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
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- 1995
(Show Context)
Citation Context ...and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous gate and wire sizing have been reported [2], [7], [8], [18], =-=[20]-=-. Chen et al. [2], Cong and Koh [8], Menezes et al. [18], and Menezes et al. [20] considered a single routing tree together Manuscript received July 22, 1998; revised November 24, 1998. This work supp... |

12 | Greedy wire-sizing is linear time
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(Show Context)
Citation Context ...ithm based on iteratively resizing the gates and wire segments. A similar technique has been successfully applied to some other wire or buffer sizing problems before (e.g., [3] and [9]). Chu and Wong =-=[5]-=- proved that for wire sizing of interconnect trees, the greedy algorithm runs in time linear to the number of segments. If we resize component (i.e., changing ) while keeping the sizes of all the othe... |

10 | Power vs. delay in gate sizing: Conflicting objectives
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(Show Context)
Citation Context ...of its size . Hence, the total dynamic power is also a linear function of . In other words, the dynamic power can be handled in exactly the same way as the total component area. Sapatnekar and Chuang =-=[21]-=- showed that the short-circuit power of gates [25] can sometimes be a nonnegligible part ofsCHEN et al: SIMULTANEOUS GATE AND WIRE SIZING BY LAGRANGIAN RELAXATION 1023 the total power dissipation. We ... |

8 |
Transistor sizing for cmos circuits
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Citation Context ... problems are of great importance. In the past, gate delay was the dominant factor in determining circuit performance. Thus, gate and transistor sizing have been extensively studied in the literature =-=[6]-=-, [12], [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [... |

3 |
TILOS: A posynominal programming approach to transistor sizing, in
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Citation Context ...lems are of great importance. In the past, gate delay was the dominant factor in determining circuit performance. Thus, gate and transistor sizing have been extensively studied in the literature [6], =-=[12]-=-, [16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9... |

2 |
RC interconnect syntheses-a moment fitting approach, in
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Citation Context ...16], [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9], =-=[19]-=-, [22]. Since gate sizes affect wire-sizing solutions and wire sizes affect gate-sizing solutions, it is beneficial to simultaneously size both gates and wires. Several results on simultaneous gate an... |

1 |
Performance optimization of digital VLSI circuits,” Stanford Univ
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Citation Context ...re of great importance. In the past, gate delay was the dominant factor in determining circuit performance. Thus, gate and transistor sizing have been extensively studied in the literature [6], [12], =-=[16]-=-, [17], [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9], [19... |

1 |
size optimization in the Tailor layout system
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Citation Context ...great importance. In the past, gate delay was the dominant factor in determining circuit performance. Thus, gate and transistor sizing have been extensively studied in the literature [6], [12], [16], =-=[17]-=-, [23]. As interconnect delay plays an increasingly important role in determining circuit performance, wire sizing has been an active research topic in the past few years [2], [4], [7], [9], [19], [22... |