Abstract

A novel library layer, called the "design space layer," is proposed, aimed at supporting both, IP-based and traditional "inhouse " design methodologies, during early design space exploration. Strategies for effectively pruning the large design spaces characteristic of system-on-chip designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is self-documented and highly compartmentalized into hierarchies of classes of design objects, and is thus easily scalable. A design space layer developed for encryption applications is presented and discussed in some detail. 1 Introduction The trend towards developing core-based, system-on-chip solutions for complex application specific systems is clearly irreversible. Increasing the level of design integration is quite attractive from a reliability, power consumption, and unit-cost perspective. The use of cores, i.e., macro-cells developed by thir...

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