Spatial Entropy - A Unified Attribute to Model Dynamic Communication in VLSI Circuits

Spatial Entropy - A Unified Attribute to Model Dynamic Communication in VLSI Circuits (1992)

Cached

Download Links

[ftp.cs.unc.edu]

by Suresh Rajgopal , Akhilesh Tyagi

BibTeX

@MISC{Rajgopal92spatialentropy,
    author = {Suresh Rajgopal and Akhilesh Tyagi},
    title = {Spatial Entropy - A Unified Attribute to Model Dynamic Communication in VLSI Circuits},
    year = {1992}
}

Bookmark

OpenURL

Abstract

This dissertation addresses the problem of capturing the dynamic communication in VLSI circuits. There are several CAD problems where attributes that combine behavior and structure are needed, or when function behavior is too complex and is best captured through some attribute in the implementation. Examples include, timing analysis, logic synthesis, dynamic power estimation, and variable ordering for binary decision diagrams (BDDs). In such a situation, using static attributes computed from the structure of the implementation is not always helpful. Firstly, they do not provide sufficient usage information, and secondly they tend to exhibit variances with implementations which is not desirable while capturing function behavior. The contribution of this research is a new circuit attribute called spatial entropy. It models the dynamic communication effort in the circuit by unifying the static structure and the dynamic data usage. Quantitatively, spatial entropy measures the switching en...

Citations

8880	Computers and Intractability: A Guide to the Theory of NPCompleteness - Garey, Johnson - 1979
4407	A mathematical theory of communication - Shannon - 1948
421	Efficient implementation of a BDD package - Brace, Rudell, et al. - 1990
342	Some complexity questions related to distributive computing - Yao - 1979
320	Logic Minimization Algorithms For VLSI Synthesis - Brayton, McMullen, et al. - 1984
312	Binary decision diagrams - Akers - 1978
305	Graph based algorithms for boolean function manipulation - Bryant - 1986
224	On the complexity of VLSI implementations and graph representation of boolean functions with application to integer multiplication - BRYANT - 1991
156	MIS: A multiple-level logic optimization system - Brayton, Rudell, et al. - 1987
132	Logic verification using binary decision diagrams in a logic synthesis environment - Malik, Wang, et al. - 1988
119	Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation - Minato, Ishiura, et al. - 1990
115	The synthesis of two terminal switching circuits - Shannon - 1949
106	On variable ordering of binary decision diagrams for the application of multi-level logic synthesis - Fujita, Matsunaga, et al. - 1991
90	Supowit : Finding an optimal variable ordering for binary decision diagrams - Friedman, J - 1990
86	The decomposition and factorization of Boolean expressions - Brayton, McMullen
86	Probabilistic Treatment of General Combinational Networks - Parker, McCluskey - 1975
83	Evaluation and improvements of boolean comparison method based on binary decision diagrams - Fujita, Fujisawa, et al. - 1988
82	Area-time complexity for VLSI - Thompson - 1979
77	Minimization of Binary Decision Diagrams Based on Exchange of Variables - Ishiura, Sawada, et al. - 1991
56	Representation of switching circuits by binary decision diagrams - Lee
37	Random pattern testability - Savir, Ditlow, et al. - 1984
35	Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams - Butler, Ross, et al. - 1991
32	An Entropy Measure for the Complexity of Multi-Output Boolean Functions," DAC-27 - Cheng, Agrawal - 1990
32	Functional approaches to generating orderings for efficient symbolic representations - Mercer, Kapur, et al. - 1992
29	Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network - McGeer, Brayton - 1989
28	Predict-probabilistic estimation of digital circuit testability - Seth, Pan, et al. - 1985
27	Introduction to the Theory of Switching Circuits - McCluskey - 1965
20	Timing Verification Using Statically Sensitizable Paths - Benkoski, Meersch, et al. - 1990
20	On the general false path problem in timing analysis - Du, Yen, et al. - 1989
20	Static Timing Analysis of Dynamically Sensitizable Paths - Perremans, Claesen, et al. - 1989
18	A Method of Fault Simulation Based on Stem Regions", Proc - Maamari, Rajski - 1990
18	Information theory and the complexity of boolean functions - Pippenger - 1977
18	Fast functional evaluation of candidate OBDD variable ordering - Ross, Butler, et al. - 1991
17	Accelerated fault simulation and fault grading in combinational circuits - Antreich, Schulz - 1987
17	Circuit Width, Register Allocation, and Ordered Binary Decision Diagrams,” in - Berman - 1991
16	Physical Design Automation of VLSI Systems - Preas, Lorenzetti - 1988
15	Stafan: An alternative to fault simulation - Jain, Agrawal - 1984
15	An Approach to Multilevel Boolean Minimization - Lawler - 1964
14	An Information Theoretic Approach to Digital Fault Testing - Agrawal - 1981
14	Testability-Driven Random Test-Pattern Generation - Lisanke, Brglez, et al. - 1987
13	Logical Network Cost and Entropy', in - Cook, Flynn - 1973
13	Variable Ordering for FSM Traversal - Jeong, Plessier, et al. - 1991
12	Multilevel Synthesis Minimizing the Routing Factor - Abouzeid, Sakouti, et al. - 1990
11	A measure of computational work - Hellerman - 1972
9	An Easily Computed Functional Level Testability Measure - Thearling, Abraham - 1989
6	Crystal: A timing analyzer for nMOS VLSI circuits - Ousterhout - 1983
5	Efficient computing communication complexity for multilevel logic synthesis - Hwang, Owens, et al. - 1992
4	A Testability Measure - Dussault - 1978
4	A Formula for Logical Network Cost - Kellerman - 1968
4	Delay Optimization of Combinational Logic Circuits through Clustering and - Touati, Savoj, et al. - 1991