A Simulation Based Study of TLB Performance (1991)
| Venue: | in The 19th Annual International Symposium on Computer Architecture |
| Citations: | 62 - 6 self |
BibTeX
@INPROCEEDINGS{Bradley91asimulation,
author = {Anita Borg Bradley and J. Bradley and Chen Norman},
title = {A Simulation Based Study of TLB Performance},
booktitle = {in The 19th Annual International Symposium on Computer Architecture},
year = {1991},
pages = {114--123}
}
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Abstract
caches. The instruction TLB should be made smaller than the data TLB, as instruction referThis paper presents the results of a simulation-based study ence streams exhibit greater locality than those of various translation lookaside buffer (TLB) architectures, for data. The appropriate size tradeoff is difin the context of a modern VLSI RISC processor. The ficult to determine and once made is fixed. If simulators used address traces, generated by instrumented the instruction TLB is too small, performance versions of the SPECmarks and several other programs run- will suffer. If it is too large, the space available for the data TLB is compromised and again per- ning on a DECstation 5000. The performance of two-level formance suffers. TLBs and fully-associative TLBs were investigated. The amount of memory mapped was found to be the dominant . Two-level TLB architectures. A small instrucfactor in TLB performance. Small first-level FIFO instruc- tion TLB (i.e., micro-TLB), can be ref...
