Abstract

Aggressive instruction scheduling is known as an effective compiler design technique that allows exploitation of instruction-level parallelisms exposed by modern processor architectures. Trace scheduling is considered to be one of the most effective acyclic global instruction scheduling methods. A trace scheduling algorithm has been developed as part of an optimizing Oberon-2 compiler for the IBM RISC System/6000. The scheduler operates on an intermediate program representation, that is based on control dependence graphs and static single assignment form. In this thesis the method of trace scheduling is discussed in the setting of this recently developed intermediate program representation and a different approach for the bookkeeping-phase of the trace scheduler is presented, which simplifies reasoning about semantic correctness of the scheduled program. Keywords Compiler Optimization, Instruction-Level Parallelism, List Scheduling, Global Instruction Scheduling, Trace Scheduling, Sp...

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