Abstract

As logic density increases, more and more functionality is moving into hardware. Several years ago, it was uncommon to find more than minimal support in a processor for integer multiplication and division. Now, several processors have multipliers included within the central processing unit on one integrated circuit [8, 12]. Integer division, due to its iterative nature, benefits much less when implemented directly in hardware and is difficult to pipeline. By using a reciprocal approximation, integer division can be synthesized from a multiply followed by a shift. Without carefully selecting the reciprocal, however, the quotient obtained often suffers from offby -one errors, requiring a correction step. This paper describes the design decisions we made when architecting integer division for a new 64 bit machine. The result is a fast and economical scheme for computing both unsigned and signed integer quotients that guarantees an exact answer without any correction. The reciprocal comput...

Citations