## Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs (2000)

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Venue: | in Proc. Int. Conf. on Computer Aided Design |

Citations: | 14 - 2 self |

### BibTeX

@INPROCEEDINGS{Cao00effectsof,

author = {Yu Cao and Chenming Hu and Xuejue Huang and Andrew B. Kahng and Sudhakar Muddu and Dirk Stroobandt and Dennis Sylvester},

title = {Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs},

booktitle = {in Proc. Int. Conf. on Computer Aided Design},

year = {2000},

pages = {56--61}

}

### OpenURL

### Abstract

In this paper, we describe optimization techniques to minimize important design objectives such as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we employ a new system-performance simulation engine, GTX (GSRC Technology Extrapolation). We concentrate on using accurate models of both circuit and design technology. For example, we take such effects as inductance, repeater staggering, signal line shielding, via parasitics, dynamic delay, and buffer placement uncertainty into account. We examine a typical critical path and apply these optimization techniques using the latest analytical models to determine their potential impact. Results indicate that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues. Also, we demonstrate that optimal wire sizing models need to consider inductive effects and use of the true worst-case capacitive noise switch factor leads to a substantial...

### Citations

133 |
Getting to the bottom of deep submicron
- Sylvester, Keutzer
(Show Context)
Citation Context ...sult, the area consumed by these buffers is substantial and may no longer be ignored during the floorplanning design phase. Particularly in a hierarchical design methodology, such as that proposed in =-=[14]-=-, it may not be possible to place repeaters at any given location either inside a pre-designed block or at the top-level of the hierarchy. A potential solution to this problem involves the formation o... |

132 |
Inductance Calculation in a complex Integrated Circuit Environment
- Ruehli
- 1972
(Show Context)
Citation Context ...oise peak because the slew times at all the nodes of the wire are faster when the line is modeled as RLC. Inductance is calculated based on expressions from [14,15] and the partial inductance concept =-=[16]-=-. We focus on analytical RLC interconnect delay models because their continuous, closed-form nature is well suited to modern iterative-improvement interconnect design methodologies and global optimiza... |

118 |
Packaging for VLSI
- Bakoglu, Circuits
- 1990
(Show Context)
Citation Context ...eral potentially important, yet previously unmodeled, optimization degrees of freedom and design constraints. For example: ♦ Previous works apply simple “optimal repeater sizing” formulae (e.g.,=-= from [1]).-=- We assess the impact of modern optimizations, notably detailed repeater size and interconnect width optimizations [9]. ♦ Since idealized formulae can result in unrealistic assumptions (extremely la... |

105 |
Closed-form expressions for interconnection delay, coupling and crosstalk in VLSI’s
- Sakurai
- 1993
(Show Context)
Citation Context ... delay of an RC line can be computed using the equation for the underdamped (real poles) case of the RLC model. The twopole RC delay is based on both coefficients b1 and b2 whereas Sakurai’s equatio=-=n [20]-=- (or Elmore delay) is based only on coefficient b1 and gives pessimistic delay results compared to the two-pole model. We have implemented three different interconnect models and compared them with HP... |

73 | Buffer block planning for interconnect-Driven floorplanning
- Cong, Kong, et al.
- 1999
(Show Context)
Citation Context ...rchy. A potential solution to this problem involves the formation of repeater block regions located around the chip at the floorplanning stage which provide specified areas for repeaters to be placed =-=[24]-=-. However, with such an approach the feasible distances between repeaters are discrete, not continuous. Here, we study the impact on critical path delay of this inability to place repeaters at arbitra... |

46 | An analytical delay model for RLC interconnects
- Kahng, Muddu
- 1997
(Show Context)
Citation Context ...RC_Bakoglu RLC_Friedman RLC_Kahng/Muddu HSPICE 2.0 4.0 6.0 8.0 10.0 Interconnect Length (mm) computed separately for the underdamped and overdamped cases. The response for these cases can be found in =-=[19]. -=-The delay of an RC line can be computed using the equation for the underdamped (real poles) case of the RLC model. The twopole RC delay is based on both coefficients b1 and b2 whereas Sakurai’s equa... |

39 |
Mobilizing the Community
- FISHER, KLING
- 1993
(Show Context)
Citation Context ...Ann Arbor. Andrew B. Kahng is now Professor of CSE and ECE at the University of California, San Diego. 1 In fact, this is basically the critical path model of [7] as well as the Roadmap: according to =-=[8]-=-, variation between 12 and 16, or between “corner-tocorner” and “chip-side length”, is what distinguishes the Roadmap's cycle time frequency predictions for ASIC, and for cost-performance and highend ... |

36 |
A Novel VLSI Layout Fabric for Deep Submicron Applications
- Khatri, Mehrotra, et al.
(Show Context)
Citation Context ...nal propagation, since wires must be thinner and more closely spaced in order to maintain a prescribed number of signal wires per unit of channel height. The extreme case of shielding is described in =-=[22]-=- where every signal wire has a ground and Vdd wire as its two nearest neighbors. In this study, we look to minimize the cost of a design while achieving good performance. The width of the shield wires... |

36 |
An efficient inductance modeling for on-chip interconnects
- He, Chang, et al.
- 1999
(Show Context)
Citation Context ...ndirectly affects the capacitive coupling noise peak because the slew times at all the nodes of the wire are faster when the line is modeled as RLC. Inductance is calculated based on expressions from =-=[14,15]-=- and the partial inductance concept [16]. We focus on analytical RLC interconnect delay models because their continuous, closed-form nature is well suited to modern iterative-improvement interconnect ... |

35 | Equivalent elmore delay for RLC trees
- Ismail, Friedman, et al.
- 2000
(Show Context)
Citation Context ...Bakoglu’s model produces matching results with HSPICE. However, when delay is more LC dominated (i.e., large inductance value), this model underestimates delay by more than 10%. Ismail et al.’s mo=-=del [24]-=- matches well with SPICE L Typically, the design guidelines will define the amount of overshoot and undershoot allowed in a response. These can be translated into a condition between the first and sec... |

30 | On Switch Factor Based Analysis of Coupled RC Interconnects
- Kahng, Muddu, et al.
- 2000
(Show Context)
Citation Context ...es. These previous works set the bounds between {0,2}; we assess the impact of using the correct bounds (for ramp input waveforms) of {-1,3} on optimal design solutions that control delay uncertainty =-=[10]. -=-♦ Previous works typically do not consider design constraints for the critical path. We assess the impact of constraints on noise margin, delay uncertainty, average wire pitch and device (repeater) ... |

27 | Layout technique for minimizing on-chip interconnect self inductance”, DAC
- Massoud, Majors, et al.
- 1998
(Show Context)
Citation Context ...ors. Nevertheless, convergent design processes require early bounds on noise and delay effects of inductance. One popular layout methodology is to insert a grounded shield wire every k routing tracks =-=[21]-=-. This can reduce worst-case inductance effects (by reducing the maximal area of the current loop, which is experienced by the middle signal wire between two consecutive grounded shield wires). On the... |

26 | Interconnect Estimation And Planning For Deep Submicron Designs
- Cong, Pan
- 1999
(Show Context)
Citation Context ...e: ♦ Previous works apply simple “optimal repeater sizing” formulae (e.g., from [1]). We assess the impact of modern optimizations, notably detailed repeater size and interconnect width optimiza=-=tions [9]. -=-♦ Since idealized formulae can result in unrealistic assumptions (extremely large repeater sizes, continuous wire tapering, etc.) we also assess the impact of engineering considerations including re... |

22 |
A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001
- Eble, De, et al.
- 1996
(Show Context)
Citation Context ...bust, portable framework for interactive specification and comparison of modeling choices (e.g., for predicting system cycle time or power dissipation). 3 Unlike previous “hard-coded” systems such=-= as [3,4,5]-=-, GTX adopts a paradigm wherein parameters and rules allow users to flexibly capture an essentially unbounded space of attributes and relationships that are germane to VLSI technology and design. User... |

18 | System-level performance modeling with BACPAC { Berkeley advanced chip performance calculator - Sylvester, Keutzer - 1999 |

17 | Performance Trends - Sai-Halasz - 1995 |

13 | GTX: The MARCO GSRC Technology Extrapolation System
- Caldwell, Kahng, et al.
(Show Context)
Citation Context ...oise, and cost. Section 6 presents conclusions and offers directions for future work. 2. STUDY IMPLEMENTATION We have conducted our studies within the MARCO GSRC Technology Extrapolation (GTX) system =-=[12,13] w-=-hich provides a robust, portable framework for interactive specification and comparison of modeling choices (e.g., for predicting system cycle time or power dissipation). 3 Unlike previous “hard-cod... |

8 |
The Test of Time: Clock-Cycle Estimation and Test Challenges for Future Microprocessors
- Fisher, Nesbitt
- 1998
(Show Context)
Citation Context ...r of EECS at the University of Michigan, Ann Arbor. Andrew B. Kahng is now Professor of CSE and ECE at the University of California, San Diego. 1 In fact, this is basically the critical path model of =-=[7]-=- as well as the Roadmap: according to [8], variation between 12 and 16, or between “corner-tocorner” and “chip-side length”, is what distinguishes the Roadmap's cycle time frequency predictions for AS... |

8 | Tuning Strategies for Global Interconnects
- Kahng, Muddu, et al.
- 1999
(Show Context)
Citation Context ... consider real-world design technology in their global interconnect models. We assess the impact of repeater staggering, and single- and double-shielding techniques, in the global interconnect design =-=[11]. 2 -=-Our work attempts to dispel some of the “vagueness” of current performance predictions that arises from the gaps noted above. We do not make any value judgments with respect to existing models; ra... |

8 | On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation - Qi, Wang, et al. - 2000 |

6 |
On Switch Factor Based Analysis
- Kahng, Muddu, et al.
(Show Context)
Citation Context ...es. These previous works set the bounds between {0,2}; we assess the impact of using the correct bounds (for ramp input waveforms) of {-1,3} on optimal design solutions that control delay uncertainty =-=[10]-=-. ♦ Previous works typically do not consider design constraints for the critical path. We assess the impact of (upper) bounds on noise margin, delay uncertainty, average wire pitch and device (repeate... |

4 | A Generic System Simulator (GENESYS - Eble, De, et al. - 1996 |

2 |
System-Level Performance Modeling with
- Sylvester, Keutzer
(Show Context)
Citation Context ...bust, portable framework for interactive specification and comparison of modeling choices (e.g., for predicting system cycle time or power dissipation). 3 Unlike previous “hard-coded” systems such=-= as [3,4,5]-=-, GTX adopts a paradigm wherein parameters and rules allow users to flexibly capture an essentially unbounded space of attributes and relationships that are germane to VLSI technology and design. User... |

2 |
et al., “Design methodology for the S/390 parallel enterprise server G4 microprocessors
- Shepard
- 1997
(Show Context)
Citation Context ...wire as a nearest neighbor, while the other neighbor is another signal wire. If signal wires are denoted by S ands2. Peak noise is fixed at 20% of Vdd and calculated based on the exponential model in =-=[23]-=-. 3. Delay uncertainty is constrained and defined to be the difference between the RC (2-pole) and RLC delays. This constraint will help minimize potential modeling errors in neglecting line inductanc... |

2 |
et al., “Design Methodology for the S/390
- Shepard
- 1997
(Show Context)
Citation Context ... 1. Maximum delay is set at 1 ns and calculated according to each of the three delay models we have incorporated. 2. Peak noise is fixed at 20% of Vdd and calculated based on the exponential model in =-=[21]-=-. 3. Delay uncertainty is constrained and defined to be the difference between the RC (2-pole) and RLC delays. This constraint helps minimize potential modeling errors in neglecting line inductance. 4... |

1 | Performance Trends in High-Performance - Sai-Halasz - 1995 |

1 | et al., "Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors - Shepard - 1997 |