## Optimizing CMOS Circuits for Low Power using Transistor Reordering (1995)

Citations: | 7 - 0 self |

### BibTeX

@MISC{Cortadella95optimizingcmos,

author = {Musoll And Cortadella},

title = {Optimizing CMOS Circuits for Low Power using Transistor Reordering},

year = {1995}

}

### OpenURL

### Abstract

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced. 1 Introduction The continuous increasing packing density and clock frequency of static CMOS circuits has pushed low power as one of the principal design parameters, specially in batterypowered portable systems, such as note-pad computers, personal digital assistants, multi-media terminals and mobile telephones. This paper addresses the optimization of a circuit for low power using transistor reordering fr...

### Citations

9049 | Introduction to Algorithms
- Cormen, Leiserson, et al.
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(Show Context)
Citation Context ... = src(e k 0 ); : : : ; dst(e kr\Gamma1 ) =src(e kr\Gamma2 ) and src(e kr\Gamma1 ) =vdd, where src(e k ) (dst(e k )) is the source (destination) node of edge e k . Using a depthfirst -search approach =-=[3]-=-, a list of all edges to visit is created (depth first search list k ). Afterwards, the edges of this list are added to the current minterm of the Hnk boolean functions(ADD INPUT TO MINTERM()) until a... |

114 |
Probabilistic treatment of general combinational networks
- PARKER, MCCLUSKEY
- 1975
(Show Context)
Citation Context ... optimization process for low power is shown in Figure 3. The probabilities for all output nodes of the gates of the circuit are computed in OBTAIN PROBABILITIES() following the algorithm proposed in =-=[7]-=-. DEPTH FIRST TRAVERSE() returns the list of gates (gate list) of the circuit (circuit) ordered in a depth-first fashion [3] from the outputs, i.e. every gate appears somewhere after all of its transi... |

107 | Transition density, a stochastic measure of activity in digital circuits
- Najm
- 1991
(Show Context)
Citation Context ...MOS gate that depends on both the static probabilities and the switching activity of its inputs. This model is based on the transition density measure of activity in digital circuits proposed by Najm =-=[6]-=-. Our power-consumption model differs from the one presented in [4] in that we take into account the switching information of the input signals. As an example, consider a 3-input NAND gate. Assume equ... |

19 |
Minimization of power in VLSI circuits using transistor sizing, input ordering and statistical power estimation
- TAN, ALLEN
- 1994
(Show Context)
Citation Context ...in the gate represented in Figure 1(a), only two different configurations are obtained by applying input reordering and four are obtained with transistor reordering. Input reordering has been used in =-=[10, 1]-=- along with transistor sizing to reduce power consumption. It is not clear in those works which is the contribution of the input reordering technique by itself. This is true specially in [1], where th... |

16 | Transistor reordering rules for power reduction in CMOS gates
- SHEN, LIN, et al.
- 1995
(Show Context)
Citation Context ... consumption of a MOSFET chain. This model accounts for the consumption of internal nodes and it depends only on the equilibrium probabilities of the inputs of the gate. The closest works to ours are =-=[8, 9]-=-. In [8], a clear example of the effect of transistor reordering on the power consumption of a circuit is shown. An estimated average of 6% in power reduction is obtained for some MCNC benchmarks. Fin... |

15 |
Circuit optimization for minimization of power consumption under delay constraint
- PRASAD, ROY
- 1994
(Show Context)
Citation Context ... consumption of a MOSFET chain. This model accounts for the consumption of internal nodes and it depends only on the equilibrium probabilities of the inputs of the gate. The closest works to ours are =-=[8, 9]-=-. In [8], a clear example of the effect of transistor reordering on the power consumption of a circuit is shown. An estimated average of 6% in power reduction is obtained for some MCNC benchmarks. Fin... |

8 |
Minimizing Power Consumption of Static CMOS Circuits by Transistor Sizing and Input Reordering
- Borah, Irwin, et al.
- 1995
(Show Context)
Citation Context ...in the gate represented in Figure 1(a), only two different configurations are obtained by applying input reordering and four are obtained with transistor reordering. Input reordering has been used in =-=[10, 1]-=- along with transistor sizing to reduce power consumption. It is not clear in those works which is the contribution of the input reordering technique by itself. This is true specially in [1], where th... |

5 |
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering
- Carlson, Chen
- 1993
(Show Context)
Citation Context ...d carry is higher (specially in those full-adders that compute the most-significant bits) because of the generation and propagation of useless signal transitions. 2 Previous work and overview Carlson =-=[2]-=- hinted the possibility to use the transistorreordering technique to decrease power consumption and he presented an algorithm for delay/power/area optimization where high speed was synonym of high pow... |

1 |
Reducing power dissipation in serially connected MOSFET circuits via transistor reordering
- Hossain, Zheng, et al.
- 1994
(Show Context)
Citation Context ...ates because these techniques focus on reducing the power consumption of the internal nodes of the gate. If the output capacitance is increased, the overall gate power reduction obtained is decreased =-=[4]-=-. Our work accounts for the transistor-reordering technique by itself. We maintain constant the size of the transistors when they are reordered in each gate. In [4], input reordering techniques are ap... |

1 |
vanGerenden.SLS: An efficient switch-level timing simulatorusing min-max voltage waveforms
- unknown authors
- 1989
(Show Context)
Citation Context ...n created. One of them contains the best transistor reordering for low power for all gates found with the optimization algorithm whereas the other one contains the worst one. A switch-level simulator =-=[11]-=- extracts the power consumption of each description. Thus, the maximum power reduction for each scenario is obtained. The input signals to the circuits used by the switch-level simulator have been gen... |

1 | Gerenden.SLS: An efficientswitch-leveltiming simulatorusing min-max voltage waveforms - van - 1989 |