Bandwidth Extension in CMOS with Optimized On-Chip Inductors (2000)
| Venue: | IEEE Journal of Solid-State Circuits |
| Citations: | 11 - 3 self |
BibTeX
@ARTICLE{Mohan00bandwidthextension,
author = {Sunderarajan S. Mohan and Maria del Mar Hershenson and Stephen P. Boyd and Thomas H. Lee},
title = {Bandwidth Extension in CMOS with Optimized On-Chip Inductors},
journal = {IEEE Journal of Solid-State Circuits},
year = {2000},
volume = {35},
pages = {346--355}
}
OpenURL
Abstract
We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k\Omega transimpedance and a 0.6- A i...







