## Design Methodologies for Noise in Digital Integrated Circuits (1998)

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Citations: | 17 - 0 self |

### BibTeX

@MISC{Shepard98designmethodologies,

author = {Kenneth L. Shepard},

title = {Design Methodologies for Noise in Digital Integrated Circuits},

year = {1998}

}

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### Abstract

In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs. 1 Introduction Noise has become a metric in the design of digital integrated circuits of comparable importance to area, timing, and power for four principle reasons: increasing interconnect densities, faster clock rates, more aggressive use of highperformance circuit families, and scaling threshold voltages. Increasing interconnect densities imply a signi#cant increase in coupling capacitance as a fraction of self-capacitance. Faster clock rates imply faster on-chip slew times. These two e#ects combine to make capacitive coupling a growing source of noise on-chip. Many high-performance circuit styles try to speed up one transition #usually falling# at the expense of the other and assign logical evaluates to the faster edge. Any circuit that utilizes these techniques we refer to as a skewed-evaluate circuit #e....

### Citations

85 |
The Design and Analysis of VLSI Circuits
- Glasser, Dobberpuhl
- 1985
(Show Context)
Citation Context ...uires that each restoring logic gate, when acted upon by a noise stimulus, must have a dc-noise time-domain sensitivity that is always less than one[1, 3]. This is a generalization of dc noise margins=-=[4]-=- to take into account the fact that restoring logic gates are much more e ect at rejecting ac noise than dc noise. It is convenient to classify noise according to the voltages' relationship to the rai... |

82 | Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
- Feldmann, Freund
- 1995
(Show Context)
Citation Context ...he number of driving ports. At these \tap points", we instead calculate a transfer frunction from each of the ports. Krylov-subspace reduced-order modelling techniques, such as Arnoldi[13] and Lanczos=-=[14]-=-, can be used to reduce these net complexes with ports and taps into hybrid admittancetransfer multiport macromodels. Because of the performance limitations of interconnect RC delays, much practical e... |

78 | White,“A Coordinate-transformed Arnoldi Algorithm for Generating Guaranteed Stable Reduced-Order Models
- Silveira, Kamon, et al.
- 1999
(Show Context)
Citation Context ...s us to reduce the number of driving ports. At these \tap points", we instead calculate a transfer frunction from each of the ports. Krylov-subspace reduced-order modelling techniques, such as Arnoldi=-=[13]-=- and Lanczos[14], can be used to reduce these net complexes with ports and taps into hybrid admittancetransfer multiport macromodels. Because of the performance limitations of interconnect RC delays, ... |

70 | Noise in deep submicron digital design
- Shepard, Narayanan
- 1996
(Show Context)
Citation Context ...ages. These e ects combine to produce more sources of on-chip noise due to switching circuits as well as less immunity to this noise. More details of these technology trends can be found in Reference =-=[1]-=-. Noise has two deleterious e ects on digital design. When noise acts against a normally static signal, it can transiently destroy the logical information carried by the static node in the circuit. If... |

58 | Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
- Dartu, Pileggi
- 1997
(Show Context)
Citation Context ... in a latch, functional failure will result. When noise acts simultaneously with a switching node, this is manifest as a change in the timing (delay and slew) of the transition (a noise-on-delay e ect=-=[2]-=-). We are concerned with the former e ect in this paper. Successful design methodologies to ensure noise immunity incorporate a three-level strategy. The rst line of defense is a set of noise avoidanc... |

33 |
et al., “A 600 MHz Superscalar RISC Microprocessor with Out-of-Order Execution
- Gieseke
- 1997
(Show Context)
Citation Context ... interconnect noise in the design of the on-chip wiring network. For example, one can increase spacing between wires or route signal lines alternately with power or ground. In the Digital 21264 design=-=[7]-=-, two metal layers are devoted exclusively for the distribution of power and ground. These ground planes more tightly control onchip inductance and reduce coupling interactions. 4 Static noise analysi... |

27 |
et al. A 200-MHz 64-b dual-issue CMOS Microprocessor
- Dobberpuhl
- 1992
(Show Context)
Citation Context ...n network and adequate decoupling capacitance. To achieve e ective supply decoupling, the ratio of on-chip decoupling capacitance to total e ective switching capacitance is generally greater than 10:1=-=[6]-=-. To control circuit and interconnect noise, circuit design rules are commonly employed. Some examples: disallow single n-FET or p-FET pass gates because of the VT voltage drop they cause; disallow pa... |

25 |
Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks
- Shepard, Narayanan, et al.
- 1997
(Show Context)
Citation Context ...net complexes and hybrid admittance-transfer multiport macromodels. The net complex as shown in Figure 9 allows one to create a local environment to analysis the coupling for a given net in the design=-=[12]-=-. The primary net of the complex is the one for which weare trying to calculate the noise. The complex also includes secondary nets with signi cant coupling to the primary net. Coupling between the si... |

12 | Adaptively Controlled Explicit Simulation - Devgan, Rohrer - 1994 |

11 |
R.: Adaptively Controlled Explicit Simulation
- Devgan, Rohrer
- 1994
(Show Context)
Citation Context ...technique: 1. Gate inputs can be replaced by grounded capacitors. This creates a clean partitioning between one CCC and the next and is a technique commonly employed in fast circuit simulation engines=-=[8]-=-. 2. Worst-case sensitization conditions drive the CCC simulations used for calculating circuit noise and interconnect noise. By this, we mean how the transistor gates are biased and internal node vol... |

9 |
Minimizing chip-level simultaneous switching noise for high-performance microprocessor design
- Chen
- 1996
(Show Context)
Citation Context ... clock activitiy. Detailed transient analysis of the power grid involves applying models of the circuits' current demands to a detailed RLC extraction of the power grid combined with the package model=-=[11, 10]-=-. The current models usually take the form of Norton equivalent circuits at designated points in the power or ground distribution hierarchy, usually on a designated via layer. (d) 1.5 2.5 (a) 0.10 Nod... |

5 |
Verity {a formal veri cation program for custom CMOS circuits
- Kuehlmann, Srinivasan, et al.
- 1995
(Show Context)
Citation Context ...propagate noise through the network, and in the case of restoring segments, to perform the sensitivity tests required to ensure noise stability. In general, transistor path-based functional extraction=-=[9]-=- guides three main types of sensitization required for Assumption 2: sensitization for coupled noise calculation on the output node of a CCC, sensitization for noise stability and propagated noise cal... |

2 |
et al. Floating-body e ects in partially depleted SOI CMOS cicuits
- Lu
- 1997
(Show Context)
Citation Context ...or charge-sharing e ects onto the output of the driving gate[1]. For silicon-on-insulator (SOI) circuits, circuit noise might also include the e ects of the parasitic bipolar in oatingbody MOS devices=-=[5]-=-, but we will not consider SOI devices 1-58113-049-x-98/0006/$3.50 35 th Design Automation Conference ® Copyright ©1998 ACM DAC98 - 06/98 San Francisco, CA USAfurther here. Interconnect noise refers ... |