Abstract

This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performance-driven routing for congestion control. Our experiments on the SUN picoJava-II TM core test circuit show that over 74% delay reduction can be achieved using our interconnect-driven floorplanner, compared to a conventional floorplanner without consideration of interconnect performance optimization/planning. We expect that IDFP with GWP will play a central role in designing interconnect-limiting, high-performance integrated circuits. 1 Introduction Global interconnect is commonly recognized as a key factor for designing high-performance integrated circuits, as VLSI process technology migrates into...

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