Abstract

Transistor size optimization is one method to reduce the power dissipation of CMOS VLSI circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum transistor sizes. The reason is that they allow for a larger reduction of the supply voltage which results in more substantial power savings. Spice simulation of prescalers with differently scaled transistors confirm the analysis. The same prescaler has been implemented in a 1.0 #m technology with minimum sized and with optimized transistors for high speed. Measurements confirm that power dissipation is reduced for optimized transistor sizes. 1 Introduction A general concern in VLSI design is power efficiency. It is indeed very obvious that battery operated equipment, such as hand-held cellular phones, laptop computers, etc. impose stringent limits on the acceptable power dissipation. It is perhaps less obvious that power efficiency is also of interest when the power suppl...

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