Abstract

We survey our recent work in the analysis and design of interconnect topologies for high-speed VLSI. Results include: a new, fast distributed RLC analysis method based on a two-pole approximation; an A-tree formulation for performance-driven interconnect; an optimal wiresizing algorithm; and new critical-path dependent routing tree algorithms. 1 Introduction Interconnection design is becoming a major concern in the design of high-speed systems, where state-of-the-art integrated circuits use submicron technology and operate at multi-giga hertz clock rates. In this range, optimization based on the traditional layout design objective, i.e. minimization of chip area, no longer suffices since the emphasis on system performance requires different consideration. For instance, the minimum Steiner tree has traditionally been the preferred interconnect topology because: (1) it uses the minimum wiring area and (2) minimum wiring area results in minimum wire capacitance, which is the dominant fac...

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