## Optimal Wiresizing Under the Distributed Elmore Delay Model (1993)

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Venue: | in Proc. Int. Conf. on Computer Aided Design |

Citations: | 53 - 26 self |

### BibTeX

@INPROCEEDINGS{Cong93optimalwiresizing,

author = {Jason Cong and Kwok-shing Leung},

title = {Optimal Wiresizing Under the Distributed Elmore Delay Model},

booktitle = {in Proc. Int. Conf. on Computer Aided Design},

year = {1993},

pages = {634--639}

}

### Years of Citing Articles

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### Abstract

In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomial-time optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in [7], our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timing-critical sinks by up to 12%. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnection delay has...

### Citations

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Citation Context ...s a strong need to develop optimal wiresizing algorithms under more accurate interconnect delay models. In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model =-=[12, 18]-=-. We have shown that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properti... |

180 | Signal delay in RC tree networks
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Citation Context ...re recently, Cong, Leung, and Zhou [7] developed an optimal wiresizing algorithm based on minimizing an upper bound of the delay in a distributed RC tree proposed by Rubinstein, Penfield and Horowitz =-=[18]-=-. In their delay model, the signal delay at any node in a distributed RC circuit is estimated by t = X all nodes k R k \Delta c k (1) where R k is the resistance between the source and the node k and ... |

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Citation Context ...reduces interconnect delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in =-=[7]-=-, our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnect delays to the timing-critical sinks by up to 12%. 1 Introduction As the VLSI fabrication te... |

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Citation Context ...uter was proposed to minimize both the cost (i.e. the total wirelength) and the radius (i.e. the longest path from the source to any sink) simultaneously. Another cost-radius tradeoff was achieved in =-=[1]-=- with further improvement in performance [3]. Both the maximum performance tree formulation in [5] and the A-tree formulation in [7] aimed at constructing a minimum wirelength routing tree which has t... |

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Citation Context ...segment (since it has the minimum total wire capacitance). Therefore, conventional global and detailed routers aimed at generating minimum-width Steiner routing trees using the least total wirelength =-=[8, 16, 4]-=-. However, as we reduce the device dimension, the driver resistance becomes smaller and the wire resistance becomes larger, which results in a much larger resistance ratio (defined to be the ratio of ... |

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Citation Context ...ongest path from the source to any sink) simultaneously. Another cost-radius tradeoff was achieved in [1] with further improvement in performance [3]. Both the maximum performance tree formulation in =-=[5]-=- and the A-tree formulation in [7] aimed at constructing a minimum wirelength routing tree which has the shortest path connection between the source and every sink. Experimental results showed that th... |

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Citation Context ...segment (since it has the minimum total wire capacitance). Therefore, conventional global and detailed routers aimed at generating minimum-width Steiner routing trees using the least total wirelength =-=[8, 16, 4]-=-. However, as we reduce the device dimension, the driver resistance becomes smaller and the wire resistance becomes larger, which results in a much larger resistance ratio (defined to be the ratio of ... |

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Citation Context ...up to 12%. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnect delay has become the dominant factor in determining circuit speed =-=[10, 19]-=-. The analysis in [21] and [7] showed that in the conventional VLSI technology, interconnect delay is determined by the product of the driver resistance and the total wire capacitance. As a result, th... |

15 |
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Citation Context ...As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnect delay has become the dominant factor in determining circuit speed [10, 19]. The analysis in =-=[21]-=- and [7] showed that in the conventional VLSI technology, interconnect delay is determined by the product of the driver resistance and the total wire capacitance. As a result, the minimum interconnect... |

13 |
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Citation Context ...n optimizing interconnect topology design for delay minimization, there were very few work on wiresizing optimization for high-performance interconnect designs. Wiresizing was used by Fisher and Kung =-=[13]-=- in H-tree clock routing. More recently, Cong, Leung, and Zhou [7] developed an optimal wiresizing algorithm based on minimizing an upper bound of the delay in a distributed RC tree proposed by Rubins... |

12 |
Pra, private communication
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Citation Context ...nology parameters are summarized in Table 3. The IC technology parameters are based on the 2��m CMOS process provided by the Robit Foresight Inc., and the MCM technology parameters were obtained f=-=rom [9]. Techno-=-logy: Integrated Circuits (ICs) Multi-Chip Modules (MCMs) Driver Resistance: 156\Omega 25\Omega Unit Wire Resistance: 0.112\Omega =��m 0.008\Omega =��m Loading Capacitance: 1 fF 1000 fF Unit W... |

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Citation Context ...(i.e. the total wirelength) and the radius (i.e. the longest path from the source to any sink) simultaneously. Another cost-radius tradeoff was achieved in [1] with further improvement in performance =-=[3]-=-. Both the maximum performance tree formulation in [5] and the A-tree formulation in [7] aimed at constructing a minimum wirelength routing tree which has the shortest path connection between the sour... |

3 |
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Citation Context ... delay to the critical sink(s) and the total wiring area of the different wiresizing solutions are compared. The signal delay is computed using the two-pole circuit simulator developed by Zhou et al. =-=[22]-=-. Extensive experimental results have shown that the two-pole simulator is comparable to SPICE in terms of delay simulation, but runs much faster [22]. Table 4 summarizes the averages of the delays an... |