## Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (1998)

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Venue: | In Proceedings of ACM/IEEE Design Automation Conference |

Citations: | 5 - 0 self |

### BibTeX

@INPROCEEDINGS{Nassif98robustelmore,

author = {Nevine Nassif and Madhav P. Desai and Dale H. Hall},

title = {Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor},

booktitle = {In Proceedings of ACM/IEEE Design Automation Conference},

year = {1998},

pages = {230--235}

}

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### Abstract

In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50# point delay of CMOS circuits in a static timing verifier. Elmore delays computed with these models fall within 10# of SPICE and can be computed thousands of times faster than if computed using SPICE. These models were used to verify critical paths during the design of a 600MHz microprocessor.

### Citations

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(Show Context)
Citation Context ...essimistic. In other words, the delays computed using the Elmore delay model have toalways be greater than those computed using a circuit simulator such as SPICE[7]. The Elmore delay which was de ned =-=[2]-=- as = Z 1 0 t dv dt (1) dt has been used extensively as a measure of delay for RC interconnect and for MOS circuits. Given an RC tree, the Elmore delay at an output node i can be computed using the fo... |

239 |
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(Show Context)
Citation Context ...to ensure that the delays were always pessimistic. In other words, the delays computed using the Elmore delay model have toalways be greater than those computed using a circuit simulator such as SPICE=-=[7]-=-. The Elmore delay which was de ned [2] as = Z 1 0 t dv dt (1) dt has been used extensively as a measure of delay for RC interconnect and for MOS circuits. Given an RC tree, the Elmore delay at an out... |

34 |
A 600MHz Superscalar RISC Microprocessor with Out-of-Order Execution
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(Show Context)
Citation Context ...ICE. These models were used to verify critical paths during the design of a 600MHz microprocessor. 1 Introduction The static timing veri er developed and used to verify the 21264 Alpha microprocessor =-=[3]-=- uses a family of delay models to compute the delay through MOS circuits. Simple complementary structures and some latches are modeled with precharacterized delays. The Elmore delay is one of the simp... |

28 |
Signal delay in general RC networks
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(Show Context)
Citation Context ...een by each device are used to approximate a MOS circuit by an RC circuit and the Elmore delay is computed. More e cient and general algorithms for computing the Elmore delay have also been developed =-=[5]-=-[6]. The resistance and capacitance models which are used to approximate the MOS circuit are a great source of error in computing the Elmore delay. We decided to focus on these models in order to impr... |

9 |
A systematic technique for verifying critical path delays in a 300MHz alpha CPU design using circuit simulation
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(Show Context)
Citation Context ... and speed (600MHz) of this CPU, it is important for us to be able to lter out as many non-violating paths as possible before having to verify them or analyze them with more time consuming algorithms =-=[1]-=-. It was, therefore, necessary for us to radically improve the accuracy of our simple delay models before resorting to more complicated models or simulation techniques. In addition, because we use the... |

8 |
Designing High Performance CMOS Microprocessors Using Full Custom
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(Show Context)
Citation Context ...through MOS circuits. Simple complementary structures and some latches are modeled with precharacterized delays. The Elmore delay is one of the simplest delay models used in the static timing veri er =-=[4]-=- and we use it to compute the delays across complex complementary structures and arbitrary non-complementary structures. We need to use the Elmore delay because many of the structures used in the Alph... |

6 |
Signal Delay inRCTree Networks
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(Show Context)
Citation Context ...dt (1) dt has been used extensively as a measure of delay for RC interconnect and for MOS circuits. Given an RC tree, the Elmore delay at an output node i can be computed using the following equation =-=[9]-=-: TDi = X k RkiCk (2) where Rki is de ned as the resistance which the two paths from the input to node i and the input to node k have in common. Equation 2 is also used to compute the Elmore delay of ... |

3 | A 600mhz Superscalar RISC Microprocessor With Out-of-Order Execution - al - 1997 |

2 |
Delay Prediction from Resistance-Capacitance Models of General MOS Circuits
- Martin, Rumin
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(Show Context)
Citation Context ... by each device are used to approximate a MOS circuit by an RC circuit and the Elmore delay is computed. More e cient and general algorithms for computing the Elmore delay have also been developed [5]=-=[6]-=-. The resistance and capacitance models which are used to approximate the MOS circuit are a great source of error in computing the Elmore delay. We decided to focus on these models in order to improve... |

2 |
A Switch-Level Timing Veri er for Digital MOS VLSI
- Ousterhout
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(Show Context)
Citation Context ...kiCk (2) where Rki is de ned as the resistance which the two paths from the input to node i and the input to node k have in common. Equation 2 is also used to compute the Elmore delay of MOS circuits =-=[8]-=-. The e ective resistance of each device and the capacitive load seen by each device are used to approximate a MOS circuit by an RC circuit and the Elmore delay is computed. More e cient and general a... |

1 |
Macromodelling of the Elmore Delay in Linear Networks for PerformanceDriven VLSI design
- Shi, Analysis
- 1993
(Show Context)
Citation Context ...e Elmore delay, ischosen so that the area under the curve vi(1) , v elmore i (t) is the same as the area under the curve vi(1),vi(t). In other words: R 1 (vi(1) , vi(t))dt 0 = (4) vi(1),vi(0) See Shi =-=[10]-=- for details. 2.2 Characterizing the Elmore Delay For a falling waveform at the output of a MOS circuit where vi(1) =0andvi(0) = VDD, the Elmore delay reduces to: R 1 vi(t)dt 0 = (5) VDD Similarly, fo... |