Abstract

Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. The methods previously proposed to address this problem suffer from problems that makes them difficult to apply on real-life large circuits. This paper presents the gate sizing algorithm GS, which has the following characteristics. It is a general purpose optimizer, e.g., it can optimize the power or/and area under some delay constraints, or the delay under some power or/and area constraints. It is oriented to a pure combinatorial optimization, and addresses non-linear, non-unimodal, constrained optimization, which enables it to handle complex cost models. It can take into account user defined or library dependent design rules. It can be applied on large circuits within a reasonable CPU time, e.g., 10000 nodes in 2 hours.

Citations

13	Gate Sizing - Berkelaar, Jess� - 1990
11	Transistor size optimization in the Tailor layout system - Marple - 1989
2	Delay Analysis of Series� Connected MOSFET Circuits - Newton� - 1991
2	An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization - Kang� - 1993
1	bert� �Input Waveform Slope E�ects - Ro� - 1990
1	Transistor Sizing for Minimizing Power Consumption - Irwin� - 1995
1	Cirit� �Transistor Sizing - A - 1987
1	Nonlinear Program� ming - McCormick� - 1968
1	Dunlop� �TILOS� a Posyno� mial Programming Approach toTransistor - E - 1985
1	LATTIS� an Iterative Speedup Heuris� tics for - Fishburn� - 1992
1	AESOP� A Tool for Automated Tran� sistor - Hedlund� - 1987
1	Schmitt�Landsiedel� �Op� timization of High�Speed CMOS Logic Circuits with Analytical Models for Signal Delay� Chip Area and Dy� namic Power Dissipation - D - 1990
1	An Algorithm for CMOS Tim� ing and Area Optimization - Soukup� - 1984
1	Najm� �A Survey of Power Estimation Techniques in VLSI Circuits - N - 1994
1	Dunlop� �Optimization�Based Transistor Sizing - E - 1988