Abstract

Reduction in leakage power has become an important concern in lowvoltage, lowpower and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using lowthreshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been veri#ed by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50#. 1 Introduction With the growing use of portable and wireless electronic systems, reduction in power consumption has become more and more importantintoday's VLSI circuit and system designs #1#, ...

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