Abstract

The shared memory programming model on top of a physically distributed memory machine (SDMM) is a promising candidate for easy-to-program general purpose parallel computation. There are, however, certain open technical problems which should be sufficiently solved before SDMM can meet the expectations. Among them is low-level structure of memory system, because most academic studies of the subject assume unrealisticly ideal memory properties, ignoring completely, e.g., the speed difference between processors and memories. In this paper we propose three memory module structures based on low-level interleaving and caching for solving this speed difference problem. We evaluate these structures along with three reference solutions by determining the overall cost factor of memory references in respect to ideal SDMM using real parallel programs. According to the evaluation the cost less than two is achieved with an interleaved solution, if proper amount of parallelism is available. Moreover,...

Citations