A Self-Reconfigurable Gate Array Architecture (2000) [5 citations — 3 self]
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author = {Reetinder Sidhu and Sameer Wadhwa and Alessandro Mei and Viktor K. Prasanna},
title = {A Self-Reconfigurable Gate Array Architecture},
year = {2000}
}
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Abstract:
. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well---no other device offers both features. The enhanced context switching feature permits arbitrary regions of the chip to selectively context switch---its not necessary for the whole device to do so. The memory access feature allows data transfer between logic cells and memory locations, and also directly between memory locations. The key innovation enabling the above features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at other nodes. The mesh of trees topology allows a logic cell to be associated with a pair of switches. The logic cell and the switches can be placed close to the memory block that ...
Citations
| 1144 | Introduction to Parallel Algorithms and Architectures: Arrays – Leighton - 1992 |
| 93 | A Time-Multiplexed FPGA – Trimberger - 1997 |
| 55 | The design and implementation of a context switching FPGA – Scalera, Vázquez - 1998 |
| 25 | String matching on multicontext FPGAs using self-reconfiguration – Sidhu, Mei, et al. - 1999 |
| 10 | Genetic programming using self-reconfigurable FPGAs – Sidhu, Mei, et al. - 1999 |
| 8 | Embedded dram for a reconfigurable array – Perissakis, Joo, et al. - 1999 |
| 7 | High-speed, hierarchical synchronous reconfigurable array – Tsu, Macy, et al. - 1999 |
