## Toward a Basis for Protocol Specification and Process Decomposition (1993)

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Venue: | in Proceedings of the IFIP Conference on Hardware Description Languages and their Applications |

Citations: | 7 - 4 self |

### BibTeX

@INPROCEEDINGS{Rath93towarda,

author = {Kamlesh Rath and Kamlesh Rath and Steven D. Johnson and Steven D. Johnson},

title = {Toward a Basis for Protocol Specification and Process Decomposition},

booktitle = {in Proceedings of the IFIP Conference on Hardware Description Languages and their Applications},

year = {1993},

pages = {157--174},

publisher = {Elsevier}

}

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### Abstract

In a formalism of top-down design, we consider the decomposition of behavioral specifications into interacting sequential components. The higher level of description specifies the operations to be performed in a major computation step. The goal is to incorporate a given interface specification in a lower-level specification that accounts for interactions with and among sequential components. This construction generalizes the earlier formalism of system factorization [14] to include interface protocols. It expands on the objectives of high-level synthesis by considering control-synchronization loops in scheduling. This paper presents a specification language for sequential process interaction and develops an interpretation based on finite-state-machines. Operations of minimization, composition and complementation are defined; the last of these being the key to top-down decomposition. A small example is used to illustrate the ideas. Keyword Codes: B.4.3; B.4.4; F.3.1 Keywords: Input/Outp...

### Citations

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Citation Context ... through iterations of collapsing equivalent states and removing redundant transitions until no states or transitions can be removed. The minimization algorithm for finite state automata described in =-=[11]-=- can be used here. 10 Two states are equivalent if all the transitions from one state have the same label and equivalent target as the transitions from the other state. Both the equivalent states are ... |

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Citation Context ...ents of sequential decomposition are bottom-up in the sense that they are oriented toward post-design verification. This would include most of the recent research in finite-state machine verification =-=[3]-=-; extensions of FSM models (e.g. [25, 24]) and Petri net theories (e.g. [2]); and model-theoretic work involving process formalisms (e.g. [20, 9]). It is typical that an area of verification research ... |

68 |
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Citation Context ...inment [7]. McMillan and Dill have also modelled timing constraints as min/max constraints and used a generalized branch and bound algorithm to verify the timing specification of connected components =-=[19]-=-. Drusinsky and Harel have used state-charts for hierarchical description for hardware and synthesis of component machines [8]. Holzmann formulated search heuristics to reduce the search space and tim... |

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Citation Context ...und algorithm to verify the timing specification of connected components [19]. Drusinsky and Harel have used state-charts for hierarchical description for hardware and synthesis of component machines =-=[8]-=-. Holzmann formulated search heuristics to reduce the search space and time for validation of communication protocols [10]. Kurshan uses L-automata with language and process homomorphism [18] to verif... |

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Citation Context ...lysis and Design Aids; Specifying and Verifying and Reasoning about Programs 1. Introduction Design derivation is a branch of formal verification that deals with "correct by construction " r=-=easoning. [12, 14, 15, 13]-=-. A system of equivalence preserving transformations are used to derive an implementation from a specification. We can view such a derivation as a formal proof reflecting a top-down reasoning style. I... |

39 | Tracing protocols
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Citation Context ... for hierarchical description for hardware and synthesis of component machines [8]. Holzmann formulated search heuristics to reduce the search space and time for validation of communication protocols =-=[10]-=-. Kurshan uses L-automata with language and process homomorphism [18] to verify reactive systems by stepwise reduction and refinement. He uses a bottomup model with registers and controllers as proces... |

30 |
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Citation Context ...Ku, Micheli [17] and Nestor et.al [22] have considered protocol-like constraints. Dill et.al have used a Buchi automata based model to verify safety and liveness properties using language containment =-=[7]-=-. McMillan and Dill have also modelled timing constraints as min/max constraints and used a generalized branch and bound algorithm to verify the timing specification of connected components [19]. Drus... |

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Citation Context ...lysis and Design Aids; Specifying and Verifying and Reasoning about Programs 1. Introduction Design derivation is a branch of formal verification that deals with "correct by construction " r=-=easoning. [12, 14, 15, 13]-=-. A system of equivalence preserving transformations are used to derive an implementation from a specification. We can view such a derivation as a formal proof reflecting a top-down reasoning style. I... |

30 |
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Citation Context ...h would have this orientation, and also that the top-down view would be better represented in synthesis research. In addition to Boriello's work (cited above), approaches to scheduling by Ku, Micheli =-=[17]-=- and Nestor et.al [22] have considered protocol-like constraints. Dill et.al have used a Buchi automata based model to verify safety and liveness properties using language containment [7]. McMillan an... |

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Citation Context ...ntation, and also that the top-down view would be better represented in synthesis research. In addition to Boriello's work (cited above), approaches to scheduling by Ku, Micheli [17] and Nestor et.al =-=[22]-=- have considered protocol-like constraints. Dill et.al have used a Buchi automata based model to verify safety and liveness properties using language containment [7]. McMillan and Dill have also model... |

18 |
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Citation Context ...interface specification in a lower-level specification that accounts for interactions with and among sequential components. This construction generalizes the earlier formalism of system factorization =-=[14]-=- to include interface protocols. It expands on the objectives of high-level synthesis by considering control-synchronization loops in scheduling. This paper presents a specification language for seque... |

11 |
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- 1989
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Citation Context ...op-down reasoning style. In this respect it should not be viewed as an alternative for deductive (i.e., conventional theorem-prover based) verification but as an alternate mode of reasoning in design =-=[16, 26]-=-. We can also view derivation as a formalization of synthesis, but as a formalization it is more centrally concerned with correctness in reasoning than with automated design. A specification can have ... |

11 |
CIRCAL: A Calculus for Circuit Description
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Citation Context ...f the recent research in finite-state machine verification [3]; extensions of FSM models (e.g. [25, 24]) and Petri net theories (e.g. [2]); and model-theoretic work involving process formalisms (e.g. =-=[20, 9]-=-). It is typical that an area of verification research would have this orientation, and also that the top-down view would be better represented in synthesis research. In addition to Boriello's work (c... |

11 |
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Citation Context ... bottom-up in the sense that they are oriented toward post-design verification. This would include most of the recent research in finite-state machine verification [3]; extensions of FSM models (e.g. =-=[25, 24]-=-) and Petri net theories (e.g. [2]); and model-theoretic work involving process formalisms (e.g. [20, 9]). It is typical that an area of verification research would have this orientation, and also tha... |

9 |
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Citation Context ...lysis and Design Aids; Specifying and Verifying and Reasoning about Programs 1. Introduction Design derivation is a branch of formal verification that deals with "correct by construction " r=-=easoning. [12, 14, 15, 13]-=-. A system of equivalence preserving transformations are used to derive an implementation from a specification. We can view such a derivation as a formal proof reflecting a top-down reasoning style. I... |

8 |
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Citation Context ...face specification, Boriello points out that, "the interface component has received limited attention even though it is crucial to integrating the circuit into an environment that will put it to =-=use" [1]-=-. However, while Boriello develops external interface specifications as a means to guide synthesis, our goal is to use them to guide design decomposition. Both sides of the protocol are involved in fa... |

6 | Algorithms for interface timing veri cation - McMillan, Dill - 1992 |

5 |
HOP: A process model for synchronous hardware; semantics and experiments in process composition
- Gopalakrishnan, Fujimoto, et al.
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Citation Context ...f the recent research in finite-state machine verification [3]; extensions of FSM models (e.g. [25, 24]) and Petri net theories (e.g. [2]); and model-theoretic work involving process formalisms (e.g. =-=[20, 9]-=-). It is typical that an area of verification research would have this orientation, and also that the top-down view would be better represented in synthesis research. In addition to Boriello's work (c... |

5 | Derivation of a DRAM memory interface by sequential decomposition
- Rath, Bose, et al.
- 1993
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Citation Context ...entation of a network of machines that implement the high-level specification. We have used process decomposition to derive a DRAM memory sub-system for an implementation of the FM9001 microprocessor =-=[23]-=-. The language described here needs to be extended to allow symbolic values on control ports. The syntax is restricted in order to maintain a simple semantics. There is no mechanism to quantify time i... |

5 |
Behavior FSMs for high-level synthesis and verification
- Takach, Wolf
- 1991
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Citation Context ... bottom-up in the sense that they are oriented toward post-design verification. This would include most of the recent research in finite-state machine verification [3]; extensions of FSM models (e.g. =-=[25, 24]-=-) and Petri net theories (e.g. [2]); and model-theoretic work involving process formalisms (e.g. [20, 9]). It is typical that an area of verification research would have this orientation, and also tha... |

4 |
Design for Verifiability
- Milne
- 1989
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Citation Context ...ocesses at the lowest level and constructs complex systems by composing them. Davie [4] takes a top-down approach to design using verification between specification and implementation steps in CIRCAL =-=[21]-=-. Design partitioning is done by description of components and composing them for verification with respect to the specification. Contextual constraints, restrictions imposed by a device on its enviro... |

3 |
A Formal, Hierarchical Design and Validation Methodology for VLSI
- Davie
- 1988
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Citation Context ...reactive systems by stepwise reduction and refinement. He uses a bottomup model with registers and controllers as processes at the lowest level and constructs complex systems by composing them. Davie =-=[4]-=- takes a top-down approach to design using verification between specification and implementation steps in CIRCAL [21]. Design partitioning is done by description of components and composing them for v... |

3 |
An Automata-Theoretic Approach to Behavioral Equivalence
- Devadas, Keutzer
- 1990
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Citation Context ...ginal fac are preserved. For simple expressions this is done by textual comparison. In general this involves verification of equivalence of logical and arithmetic expressions, and is a heuristic task =-=[6]-=-. Letsu,sv be the values in registers u, v before the procedures u = u \Gamma 1 and v = usv in the original fac. The values in the registers after the procedures in the original fac and by scheduling ... |

3 |
An example of digital design transformation in an algebraic framework
- Zhu, Johnson
- 1991
(Show Context)
Citation Context ...op-down reasoning style. In this respect it should not be viewed as an alternative for deductive (i.e., conventional theorem-prover based) verification but as an alternate mode of reasoning in design =-=[16, 26]-=-. We can also view derivation as a formalization of synthesis, but as a formalization it is more centrally concerned with correctness in reasoning than with automated design. A specification can have ... |

3 | On the interplay of synthesis and veri cation: Experiments with the FM8501 processor description - Johnson, Wehrmeister, et al. - 1989 |

2 |
Synthesis of Self- Timed VLSI Circuits from Graph-Theoretic Specifications
- Chu
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(Show Context)
Citation Context ...riented toward post-design verification. This would include most of the recent research in finite-state machine verification [3]; extensions of FSM models (e.g. [25, 24]) and Petri net theories (e.g. =-=[2]-=-); and model-theoretic work involving process formalisms (e.g. [20, 9]). It is typical that an area of verification research would have this orientation, and also that the top-down view would be bette... |

2 |
Analysis of discrete event simulation
- Kurshan
- 1989
(Show Context)
Citation Context ... machines [8]. Holzmann formulated search heuristics to reduce the search space and time for validation of communication protocols [10]. Kurshan uses L-automata with language and process homomorphism =-=[18]-=- to verify reactive systems by stepwise reduction and refinement. He uses a bottomup model with registers and controllers as processes at the lowest level and constructs complex systems by composing t... |

2 | An Automata-Theoretic Approach toBehavioral Equivalence - Devadas, Keutzer - 1990 |

1 |
Contextual constraints for design and verification
- Davie, Milne
- 1988
(Show Context)
Citation Context ...ts environment, are introduced to write partial specifications of a component's environment. The constraints are also used to restrict the target architecture to reduce the complexity of verification =-=[5]-=-. A CIRCAL 2 based transformation to partition a design is mentioned. The designer specifies a component and an algorithm is used to generate the specification of the other component(s) in the design.... |

1 | Speci cation and synthesis of interface logic - Borriello - 1991 |

1 | Contextual constraints for design and veri cation - Davie, Milne - 1988 |

1 | Design for veri ability - Milne - 1989 |

1 | andWayne Wolf. Behavior FSMs for high-level synthesis and veri cation - Takach - 1991 |