Abstract

We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid. In this paper we formulate the gate sizing problem for gate sizing for minimal power while removing glitches. We take into account both dynamic power dissipation as well as short-circuit power dissipation. To remove glitches we introduce additional constraints. We discuss the merits of the formulation and the problems encountered ...

Citations