A Scalable Approach to Thread-Level Speculation

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A Scalable Approach to Thread-Level Speculation (2000)

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by J. Gregory Steffan , Christopher B. Colohan , Antonia Zhai , Todd C. Mowry

Venue:	IN PROCEEDINGS OF THE 27TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
Citations:	232 - 20 self

BibTeX

@INPROCEEDINGS{Steffan00ascalable,
    author = {J. Gregory Steffan and Christopher B. Colohan and Antonia Zhai and Todd C. Mowry},
    title = {A Scalable Approach to Thread-Level Speculation},
    booktitle = {IN PROCEEDINGS OF THE 27TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE},
    year = {2000},
    pages = {1--12},
    publisher = {}
}

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Abstract

While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performancepotential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.

Keyphrases

thread-level speculation scalable approach machine size wide spectrum single-chip multiprocessor straightforward extension large-scale server parallel software parallel thread scheme performs cost-effective parallel machine single chip real challenge raw performancepotential larger-scale machine twenty time experimental result promising technique writeback invalidation-based cache coherence communication latency

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