Optimization of Custom MOS Circuits by Transistor Sizing (1996)
| Venue: | IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN |
| Citations: | 9 - 4 self |
BibTeX
@INPROCEEDINGS{Conn96optimizationof,
author = {Andrew R. Conn and Paula K. Coulman and Ruud A. Haring and Gregory L. Morrill and Chandu Visweswariah},
title = {Optimization of Custom MOS Circuits by Transistor Sizing},
booktitle = {IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN},
year = {1996},
pages = {174--180},
publisher = {}
}
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Abstract
Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses
