Analysis and Design of Multiple-Bit High-Order \Sigma-\Delta Modulator (1997)
| Venue: | 566 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 9, SEPTEMBER 2003 [13 |
| Citations: | 1 - 1 self |
BibTeX
@INPROCEEDINGS{Hong97analysisand,
author = {Hao-chiao Hong and Bin-Hong Lin and Cheng-Wen Wu},
title = {Analysis and Design of Multiple-Bit High-Order \Sigma-\Delta Modulator},
booktitle = {566 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 9, SEPTEMBER 2003 [13},
year = {1997},
pages = {419--424}
}
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Abstract
The high-order \Sigma-\Delta modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order \Sigma-\Delta architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations. I. Introduction The A/D converter is an important element for digitalsignal processing systems. The cruxes of an A/D converter are high resolution for precise representation of the original signal and high bandwidth for fast processing. Conventional A/D architectures, e.g., flash, 2-step flash, and successive approximation, are not suitable for highresolution applications because of the need of near-ideal analog component...
